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| author | Peter Maydell <peter.maydell@linaro.org> | 2019-05-21 19:56:47 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2019-05-21 19:56:47 +0100 |
| commit | 542ad0eb9571577107c125079fa11eaa368363f4 (patch) | |
| tree | 8b59f49c7614cde9d0051d747af04cfb3d59d0f5 | |
| parent | a4f667b6714916683408b983cfe0a615a725775f (diff) | |
| parent | 20140a82c67467f53814ca197403d5e1b561a5e5 (diff) | |
| download | qemu-542ad0eb9571577107c125079fa11eaa368363f4.zip qemu-542ad0eb9571577107c125079fa11eaa368363f4.tar.gz qemu-542ad0eb9571577107c125079fa11eaa368363f4.tar.bz2 | |
Merge remote-tracking branch 'remotes/ehabkost/tags/x86-next-pull-request' into staging
x86 MDS feature flags
md-clear and mds-no feature flags, for detection and mitigation
of MDS vulnerabilities (CVE-2018-12126, CVE-2018-12127,
CVE-2018-12130, CVE-2019-11091).
# gpg: Signature made Tue 21 May 2019 19:42:43 BST
# gpg: using RSA key 2807936F984DC5A6
# gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" [full]
# Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF D1AA 2807 936F 984D C5A6
* remotes/ehabkost/tags/x86-next-pull-request:
target/i386: add MDS-NO feature
docs: recommend use of md-clear feature on all Intel CPUs
target/i386: define md-clear bit
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | docs/qemu-cpu-models.texi | 12 | ||||
| -rw-r--r-- | target/i386/cpu.c | 4 |
2 files changed, 14 insertions, 2 deletions
diff --git a/docs/qemu-cpu-models.texi b/docs/qemu-cpu-models.texi index 23c11dc..ad040cf 100644 --- a/docs/qemu-cpu-models.texi +++ b/docs/qemu-cpu-models.texi @@ -200,6 +200,18 @@ Not included by default in any Intel CPU model. Should be explicitly turned on for all Intel CPU models. Note that not all CPU hardware will support this feature. + +@item @code{md-clear} + +Required to confirm the MDS (CVE-2018-12126, CVE-2018-12127, CVE-2018-12130, +CVE-2019-11091) fixes. + +Not included by default in any Intel CPU model. + +Must be explicitly turned on for all Intel CPU models. + +Requires the host CPU microcode to support this feature before it +can be used for guest CPUs. @end table diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 2df56fa..2f151da 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1077,7 +1077,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { .feat_names = { NULL, NULL, "avx512-4vnniw", "avx512-4fmaps", NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL, + NULL, NULL, "md-clear", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, @@ -1184,7 +1184,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { .type = MSR_FEATURE_WORD, .feat_names = { "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry", - "ssb-no", NULL, NULL, NULL, + "ssb-no", "mds-no", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, |