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| author | Alexey Baturo <baturo.alexey@gmail.com> | 2021-10-25 20:36:02 +0300 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2021-10-28 14:39:23 +1000 |
| commit | 53dcea58b8ab150ab034f9c19074c5f74d6ca41e (patch) | |
| tree | 2ee3eb177cc4c82e32e7179d12b2a32377c755ca | |
| parent | 9b144ed444f1fb3149d9ec17f0c4a64d4fd7d662 (diff) | |
| download | qemu-53dcea58b8ab150ab034f9c19074c5f74d6ca41e.zip qemu-53dcea58b8ab150ab034f9c19074c5f74d6ca41e.tar.gz qemu-53dcea58b8ab150ab034f9c19074c5f74d6ca41e.tar.bz2 | |
target/riscv: Add J-extension into RISC-V
Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20211025173609.2724490-2-space.monkey.delivers@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| -rw-r--r-- | target/riscv/cpu.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index a33dc30..1cfc6a5 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -65,6 +65,7 @@ #define RVS RV('S') #define RVU RV('U') #define RVH RV('H') +#define RVJ RV('J') /* S extension denotes that Supervisor mode exists, however it is possible to have a core that support S mode but does not have an MMU and there @@ -291,6 +292,7 @@ struct RISCVCPU { bool ext_s; bool ext_u; bool ext_h; + bool ext_j; bool ext_v; bool ext_zba; bool ext_zbb; |