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author | Andreas Färber <andreas.faerber@web.de> | 2013-06-30 21:20:26 +0200 |
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committer | Andreas Färber <afaerber@suse.de> | 2013-11-05 17:47:30 +0100 |
commit | 524a2d8e2628b3241f0dcaa6a96d57e8120cc439 (patch) | |
tree | 7480af35304173f02665eb72d711883a43fcde0c | |
parent | b9ed148d243839aba3864b4419114396f6fda2fc (diff) | |
download | qemu-524a2d8e2628b3241f0dcaa6a96d57e8120cc439.zip qemu-524a2d8e2628b3241f0dcaa6a96d57e8120cc439.tar.gz qemu-524a2d8e2628b3241f0dcaa6a96d57e8120cc439.tar.bz2 |
a15mpcore: Embed GICState
This covers both emulated and KVM GIC.
Prepares for QOM realize.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Andreas Färber <andreas.faerber@web.de>
-rw-r--r-- | hw/cpu/a15mpcore.c | 39 |
1 files changed, 24 insertions, 15 deletions
diff --git a/hw/cpu/a15mpcore.c b/hw/cpu/a15mpcore.c index af29c35..b2614e7 100644 --- a/hw/cpu/a15mpcore.c +++ b/hw/cpu/a15mpcore.c @@ -20,6 +20,7 @@ #include "hw/sysbus.h" #include "sysemu/kvm.h" +#include "hw/intc/arm_gic.h" /* A15MP private memory region. */ @@ -35,41 +36,49 @@ typedef struct A15MPPrivState { uint32_t num_cpu; uint32_t num_irq; MemoryRegion container; - DeviceState *gic; + + GICState gic; } A15MPPrivState; static void a15mp_priv_set_irq(void *opaque, int irq, int level) { A15MPPrivState *s = (A15MPPrivState *)opaque; - qemu_set_irq(qdev_get_gpio_in(s->gic, irq), level); + + qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level); } static void a15mp_priv_initfn(Object *obj) { SysBusDevice *sbd = SYS_BUS_DEVICE(obj); A15MPPrivState *s = A15MPCORE_PRIV(obj); + DeviceState *gicdev; + const char *gictype = "arm_gic"; + + if (kvm_irqchip_in_kernel()) { + gictype = "kvm-arm-gic"; + } memory_region_init(&s->container, obj, "a15mp-priv-container", 0x8000); sysbus_init_mmio(sbd, &s->container); + + object_initialize(&s->gic, sizeof(s->gic), gictype); + gicdev = DEVICE(&s->gic); + qdev_set_parent_bus(gicdev, sysbus_get_default()); + qdev_prop_set_uint32(gicdev, "revision", 2); } static int a15mp_priv_init(SysBusDevice *dev) { A15MPPrivState *s = A15MPCORE_PRIV(dev); + DeviceState *gicdev; SysBusDevice *busdev; - const char *gictype = "arm_gic"; int i; - if (kvm_irqchip_in_kernel()) { - gictype = "kvm-arm-gic"; - } - - s->gic = qdev_create(NULL, gictype); - qdev_prop_set_uint32(s->gic, "num-cpu", s->num_cpu); - qdev_prop_set_uint32(s->gic, "num-irq", s->num_irq); - qdev_prop_set_uint32(s->gic, "revision", 2); - qdev_init_nofail(s->gic); - busdev = SYS_BUS_DEVICE(s->gic); + gicdev = DEVICE(&s->gic); + qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu); + qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq); + qdev_init_nofail(gicdev); + busdev = SYS_BUS_DEVICE(&s->gic); /* Pass through outbound IRQ lines from the GIC */ sysbus_pass_irq(dev, busdev); @@ -87,10 +96,10 @@ static int a15mp_priv_init(SysBusDevice *dev) * since a real A15 always has TrustZone but QEMU doesn't. */ qdev_connect_gpio_out(cpudev, 0, - qdev_get_gpio_in(s->gic, ppibase + 30)); + qdev_get_gpio_in(gicdev, ppibase + 30)); /* virtual timer */ qdev_connect_gpio_out(cpudev, 1, - qdev_get_gpio_in(s->gic, ppibase + 27)); + qdev_get_gpio_in(gicdev, ppibase + 27)); } /* Memory map (addresses are offsets from PERIPHBASE): |