diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2020-09-10 18:38:54 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2020-10-01 15:31:00 +0100 |
| commit | 51cb228a1d1c0e325b4e7dea0bfb3140d6d11422 (patch) | |
| tree | 8e4ce18682c9447df73be04a2e2b5104a7b96f38 | |
| parent | d20c3ebda2972255e67c0a07368ac37f37a16c04 (diff) | |
| download | qemu-51cb228a1d1c0e325b4e7dea0bfb3140d6d11422.zip qemu-51cb228a1d1c0e325b4e7dea0bfb3140d6d11422.tar.gz qemu-51cb228a1d1c0e325b4e7dea0bfb3140d6d11422.tar.bz2 | |
target/arm: Add ID register values for Cortex-M0
Give the Cortex-M0 ID register values corresponding to its
implemented behaviour. These will not be guest-visible but will be
used to govern the behaviour of QEMU's emulation. We use the same
values that the Cortex-M3 does.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200910173855.4068-5-peter.maydell@linaro.org
| -rw-r--r-- | target/arm/cpu_tcg.c | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index a9b7cf5..0013e25 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -256,6 +256,30 @@ static void cortex_m0_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_M); cpu->midr = 0x410cc200; + + /* + * These ID register values are not guest visible, because + * we do not implement the Main Extension. They must be set + * to values corresponding to the Cortex-M0's implemented + * features, because QEMU generally controls its emulation + * by looking at ID register fields. We use the same values as + * for the M3. + */ + cpu->isar.id_pfr0 = 0x00000030; + cpu->isar.id_pfr1 = 0x00000200; + cpu->isar.id_dfr0 = 0x00100000; + cpu->id_afr0 = 0x00000000; + cpu->isar.id_mmfr0 = 0x00000030; + cpu->isar.id_mmfr1 = 0x00000000; + cpu->isar.id_mmfr2 = 0x00000000; + cpu->isar.id_mmfr3 = 0x00000000; + cpu->isar.id_isar0 = 0x01141110; + cpu->isar.id_isar1 = 0x02111000; + cpu->isar.id_isar2 = 0x21112231; + cpu->isar.id_isar3 = 0x01111110; + cpu->isar.id_isar4 = 0x01310102; + cpu->isar.id_isar5 = 0x00000000; + cpu->isar.id_isar6 = 0x00000000; } static void cortex_m3_initfn(Object *obj) |