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| author | Jamin Lin <jamin_lin@aspeedtech.com> | 2025-06-18 16:00:04 +0800 |
|---|---|---|
| committer | Cédric Le Goater <clg@redhat.com> | 2025-07-03 13:41:57 +0200 |
| commit | 51ac481bff88723ef4c101925082fab03bba200a (patch) | |
| tree | c3d71e283097cd94fe0bd1090240d1164157d82a | |
| parent | c77283dd5d79149f4e7e9edd00f65416c648ee59 (diff) | |
| download | qemu-51ac481bff88723ef4c101925082fab03bba200a.zip qemu-51ac481bff88723ef4c101925082fab03bba200a.tar.gz qemu-51ac481bff88723ef4c101925082fab03bba200a.tar.bz2 | |
hw/misc/aspeed_sdmc: Skipping dram_init in u-boot for AST2700
On AST2700 SoC, QEMU now sets BIT6 in VGA0 SCRATCH register to indicate
that DDR training has completed, thus skipping the dram_init().
To align with the recent U-Boot changes, where the Main Control Register's
BIT16 is checked to skip the dram_init() process, this patch sets BIT16 in
the SDMC Main Control Register at reset time.
This allows both the main U-Boot stage to correctly detect and bypass DRAM
initialization when running under QEMU.
Reference:
- QEMU: https://github.com/qemu/qemu/commit/2d082fea485ee455a70ed3e963cdf9a70f34858a
- U-Boot: https://github.com/AspeedTech-BMC/u-boot/commit/94e5435504fb0d8888f5c1bfd3fa284cdd6aaf9b
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20250618080006.846355-2-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
| -rw-r--r-- | hw/misc/aspeed_sdmc.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c index f04d993..dff7cc3 100644 --- a/hw/misc/aspeed_sdmc.c +++ b/hw/misc/aspeed_sdmc.c @@ -570,6 +570,9 @@ static void aspeed_2700_sdmc_reset(DeviceState *dev) /* Set ram size bit and defaults values */ s->regs[R_MAIN_CONF] = asc->compute_conf(s, 0); + /* Skipping dram init */ + s->regs[R_MAIN_CONTROL] = BIT(16); + if (s->unlocked) { s->regs[R_2700_PROT] = PROT_UNLOCKED; } |