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| author | Bin Meng <bmeng.cn@gmail.com> | 2019-03-17 01:03:10 -0700 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@sifive.com> | 2019-03-19 05:18:28 -0700 |
| commit | 4e85ea82c1b2cd7c27970b671cd4ca6ef6f78354 (patch) | |
| tree | c90e5a7136ad8049b0de03d2ade72a1f8969ce7e | |
| parent | 6b745d4fada5c73db44f596a62e29a5dbe3fc53f (diff) | |
| download | qemu-4e85ea82c1b2cd7c27970b671cd4ca6ef6f78354.zip qemu-4e85ea82c1b2cd7c27970b671cd4ca6ef6f78354.tar.gz qemu-4e85ea82c1b2cd7c27970b671cd4ca6ef6f78354.tar.bz2 | |
riscv: sifive_uart: Generate TX interrupt
At present the sifive uart model only generates RX interrupt. This
updates it to generate TX interrupt so that it is more useful.
Note the TX fifo is still unimplemented.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
| -rw-r--r-- | hw/riscv/sifive_uart.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/hw/riscv/sifive_uart.c b/hw/riscv/sifive_uart.c index 456a3d3..3b3f94f 100644 --- a/hw/riscv/sifive_uart.c +++ b/hw/riscv/sifive_uart.c @@ -51,7 +51,8 @@ static uint64_t uart_ip(SiFiveUARTState *s) static void update_irq(SiFiveUARTState *s) { int cond = 0; - if ((s->ie & SIFIVE_UART_IE_RXWM) && s->rx_fifo_len) { + if ((s->ie & SIFIVE_UART_IE_TXWM) || + ((s->ie & SIFIVE_UART_IE_RXWM) && s->rx_fifo_len)) { cond = 1; } if (cond) { @@ -108,6 +109,7 @@ uart_write(void *opaque, hwaddr addr, switch (addr) { case SIFIVE_UART_TXFIFO: qemu_chr_fe_write(&s->chr, &ch, 1); + update_irq(s); return; case SIFIVE_UART_IE: s->ie = val64; |