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| author | Jason Chien <jason.chien@sifive.com> | 2024-03-28 10:23:12 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2024-06-03 11:12:12 +1000 |
| commit | 4a90991234f003d8fe55919e84bf3ec7d542830e (patch) | |
| tree | 148184a9509ec657a3175b7e21997484ccea0ef0 | |
| parent | e7dc5e160f69678432c24827b522baf82b73688a (diff) | |
| download | qemu-4a90991234f003d8fe55919e84bf3ec7d542830e.zip qemu-4a90991234f003d8fe55919e84bf3ec7d542830e.tar.gz qemu-4a90991234f003d8fe55919e84bf3ec7d542830e.tar.bz2 | |
target/riscv: Relax vector register check in RISCV gdbstub
In current implementation, the gdbstub allows reading vector registers
only if V extension is supported. However, all vector extensions and
vector crypto extensions have the vector registers and they all depend
on Zve32x. The gdbstub should check for Zve32x instead.
Signed-off-by: Jason Chien <jason.chien@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Max Chou <max.chou@sifive.com>
Message-ID: <20240328022343.6871-4-jason.chien@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| -rw-r--r-- | target/riscv/gdbstub.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index be7a02c..d0cc576 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -338,7 +338,7 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) gdb_find_static_feature("riscv-32bit-fpu.xml"), 0); } - if (env->misa_ext & RVV) { + if (cpu->cfg.ext_zve32x) { gdb_register_coprocessor(cs, riscv_gdb_get_vector, riscv_gdb_set_vector, ricsv_gen_dynamic_vector_feature(cs, cs->gdb_num_regs), |