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authorHao Wu <wuhaotsh@google.com>2022-07-14 11:28:31 -0700
committerPeter Maydell <peter.maydell@linaro.org>2022-07-18 13:20:14 +0100
commit4a84e85413acaad9e84b64786e44e190080d78a6 (patch)
treeb00ee7a758880526461d79c168a121a89b036fd0
parentf04383e74926180cc56809ec8319115e4cea32b7 (diff)
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hw/adc: Fix CONV bit in NPCM7XX ADC CON register
The correct bit for the CONV bit in NPCM7XX ADC is bit 13. This patch fixes that in the module, and also lower the IRQ when the guest is done handling an interrupt event from the ADC module. Signed-off-by: Hao Wu <wuhaotsh@google.com> Reviewed-by: Patrick Venture<venture@google.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20220714182836.89602-4-wuhaotsh@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-rw-r--r--hw/adc/npcm7xx_adc.c2
-rw-r--r--tests/qtest/npcm7xx_adc-test.c2
2 files changed, 2 insertions, 2 deletions
diff --git a/hw/adc/npcm7xx_adc.c b/hw/adc/npcm7xx_adc.c
index 0f0a9f6..47fb9e5 100644
--- a/hw/adc/npcm7xx_adc.c
+++ b/hw/adc/npcm7xx_adc.c
@@ -36,7 +36,7 @@ REG32(NPCM7XX_ADC_DATA, 0x4)
#define NPCM7XX_ADC_CON_INT BIT(18)
#define NPCM7XX_ADC_CON_EN BIT(17)
#define NPCM7XX_ADC_CON_RST BIT(16)
-#define NPCM7XX_ADC_CON_CONV BIT(14)
+#define NPCM7XX_ADC_CON_CONV BIT(13)
#define NPCM7XX_ADC_CON_DIV(rv) extract32(rv, 1, 8)
#define NPCM7XX_ADC_MAX_RESULT 1023
diff --git a/tests/qtest/npcm7xx_adc-test.c b/tests/qtest/npcm7xx_adc-test.c
index 3fa6d9e..8048044 100644
--- a/tests/qtest/npcm7xx_adc-test.c
+++ b/tests/qtest/npcm7xx_adc-test.c
@@ -50,7 +50,7 @@
#define CON_INT BIT(18)
#define CON_EN BIT(17)
#define CON_RST BIT(16)
-#define CON_CONV BIT(14)
+#define CON_CONV BIT(13)
#define CON_DIV(rv) extract32(rv, 1, 8)
#define FST_RDST BIT(1)