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| author | Alistair Francis <Alistair.Francis@wdc.com> | 2019-04-20 02:27:10 +0000 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@sifive.com> | 2019-05-24 12:09:24 -0700 |
| commit | 49aaa3e534f5422a56313bb93c1880e70fc1da7e (patch) | |
| tree | 2c8d0addff82857db3ffb3534264520ad029994d | |
| parent | 16fdb8ff64374ed51b246437e13043039a8eb9f9 (diff) | |
| download | qemu-49aaa3e534f5422a56313bb93c1880e70fc1da7e.zip qemu-49aaa3e534f5422a56313bb93c1880e70fc1da7e.tar.gz qemu-49aaa3e534f5422a56313bb93c1880e70fc1da7e.tar.bz2 | |
target/riscv: Add the MPV and MTL mstatus bits
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
| -rw-r--r-- | target/riscv/cpu_bits.h | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 945aa8d..fe71647 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -316,14 +316,11 @@ /* mstatus CSR bits */ #define MSTATUS_UIE 0x00000001 #define MSTATUS_SIE 0x00000002 -#define MSTATUS_HIE 0x00000004 #define MSTATUS_MIE 0x00000008 #define MSTATUS_UPIE 0x00000010 #define MSTATUS_SPIE 0x00000020 -#define MSTATUS_HPIE 0x00000040 #define MSTATUS_MPIE 0x00000080 #define MSTATUS_SPP 0x00000100 -#define MSTATUS_HPP 0x00000600 #define MSTATUS_MPP 0x00001800 #define MSTATUS_FS 0x00006000 #define MSTATUS_XS 0x00018000 @@ -335,6 +332,8 @@ #define MSTATUS_TVM 0x00100000 /* since: priv-1.10 */ #define MSTATUS_TW 0x20000000 /* since: priv-1.10 */ #define MSTATUS_TSR 0x40000000 /* since: priv-1.10 */ +#define MSTATUS_MTL 0x4000000000ULL +#define MSTATUS_MPV 0x8000000000ULL #define MSTATUS64_UXL 0x0000000300000000ULL #define MSTATUS64_SXL 0x0000000C00000000ULL |