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authorJonathan Cameron <Jonathan.Cameron@huawei.com>2024-01-26 12:01:29 +0000
committerMichael S. Tsirkin <mst@redhat.com>2024-02-14 06:09:32 -0500
commit48461825af1bdc68cfa25fa0b698c958b65f7368 (patch)
tree74b62e67e69e17deb0b5a931e06c710a6b99bd64
parentf8b02dd655cc20ca7f321c42acbffb143eb8372a (diff)
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hw/mem/cxl_type3: Fix potential divide by zero reported by coverity
Fixes Coverity ID 1522368. Currently error_fatal is set if interleave_ways_dec() is going to return 0 but we should handle that zero return explicitly. Reported-by: Stefan Hajnoczi <stefanha@gmail.com> Reviewed-by: Fan Ni <fan.ni@samsung.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20240126120132.24248-10-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
-rw-r--r--hw/mem/cxl_type3.c9
1 files changed, 7 insertions, 2 deletions
diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
index 1b92a06..71fcb44 100644
--- a/hw/mem/cxl_type3.c
+++ b/hw/mem/cxl_type3.c
@@ -794,8 +794,13 @@ static bool cxl_type3_dpa(CXLType3Dev *ct3d, hwaddr host_addr, uint64_t *dpa)
}
if (((uint64_t)host_addr < decoder_base) ||
(hpa_offset >= decoder_size)) {
- dpa_base += decoder_size /
- cxl_interleave_ways_dec(iw, &error_fatal);
+ int decoded_iw = cxl_interleave_ways_dec(iw, &error_fatal);
+
+ if (decoded_iw == 0) {
+ return false;
+ }
+
+ dpa_base += decoder_size / decoded_iw;
continue;
}