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| author | Sergey Makarov <s.makarov@syntacore.com> | 2024-09-18 17:02:28 +0300 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2024-10-30 11:22:07 +1000 |
| commit | 41fc1f02947dd7a33b2c1d0e8474744b12f2514e (patch) | |
| tree | d9407fb5f448e39c53c03eaac2168ff76649a419 | |
| parent | bfd12c92cc77a3def85c18157f5dbc198c062609 (diff) | |
| download | qemu-41fc1f02947dd7a33b2c1d0e8474744b12f2514e.zip qemu-41fc1f02947dd7a33b2c1d0e8474744b12f2514e.tar.gz qemu-41fc1f02947dd7a33b2c1d0e8474744b12f2514e.tar.bz2 | |
hw/intc: Make zeroth priority register read-only
According to PLIC specification chapter 4, zeroth
priority register is reserved. Discard writes to
this register.
Signed-off-by: Sergey Makarov <s.makarov@syntacore.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240918140229.124329-2-s.makarov@syntacore.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| -rw-r--r-- | hw/intc/sifive_plic.c | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c index 7f43e96..8de3a65 100644 --- a/hw/intc/sifive_plic.c +++ b/hw/intc/sifive_plic.c @@ -189,8 +189,13 @@ static void sifive_plic_write(void *opaque, hwaddr addr, uint64_t value, if (addr_between(addr, plic->priority_base, plic->num_sources << 2)) { uint32_t irq = (addr - plic->priority_base) >> 2; - - if (((plic->num_priorities + 1) & plic->num_priorities) == 0) { + if (irq == 0) { + /* IRQ 0 source prioority is reserved */ + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Invalid source priority write 0x%" + HWADDR_PRIx "\n", __func__, addr); + return; + } else if (((plic->num_priorities + 1) & plic->num_priorities) == 0) { /* * if "num_priorities + 1" is power-of-2, make each register bit of * interrupt priority WARL (Write-Any-Read-Legal). Just filter |