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| author | Jonathan Cameron <Jonathan.Cameron@huawei.com> | 2024-01-26 12:16:33 +0000 |
|---|---|---|
| committer | Michael S. Tsirkin <mst@redhat.com> | 2024-02-14 06:09:32 -0500 |
| commit | 40ecac10c03aa74deada32a1ee7af1ad9750d483 (patch) | |
| tree | a3218e858d4082bef3f0a5db674ed507ceca483b | |
| parent | ae243dbfc45eb6d91b34d0ecb73b104a9ee0d058 (diff) | |
| download | qemu-40ecac10c03aa74deada32a1ee7af1ad9750d483.zip qemu-40ecac10c03aa74deada32a1ee7af1ad9750d483.tar.gz qemu-40ecac10c03aa74deada32a1ee7af1ad9750d483.tar.bz2 | |
hw/cxl: Update link register definitions.
Not actually implemented, but we need to reserve more space for
the larger version of the structure in CXL r3.1.
Reviewed-by: Fan Ni <fan.ni@samsung.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20240126121636.24611-3-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
| -rw-r--r-- | include/hw/cxl/cxl_component.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/include/hw/cxl/cxl_component.h b/include/hw/cxl/cxl_component.h index 7d3edef..2c7631b 100644 --- a/include/hw/cxl/cxl_component.h +++ b/include/hw/cxl/cxl_component.h @@ -104,10 +104,10 @@ REG32(CXL_RAS_ERR_HEADER0, CXL_RAS_REGISTERS_OFFSET + 0x18) (CXL_RAS_REGISTERS_OFFSET + CXL_RAS_REGISTERS_SIZE) #define CXL_SEC_REGISTERS_SIZE 0 /* We don't implement 1.1 downstream ports */ -/* 8.2.5.11 - CXL Link Capability Structure */ +/* CXL r3.1 Section 8.2.4.19: CXL Link Capability Structure */ #define CXL_LINK_REGISTERS_OFFSET \ (CXL_SEC_REGISTERS_OFFSET + CXL_SEC_REGISTERS_SIZE) -#define CXL_LINK_REGISTERS_SIZE 0x38 +#define CXL_LINK_REGISTERS_SIZE 0x50 /* CXL r3.1 Section 8.2.4.20: CXL HDM Decoder Capability Structure */ #define HDM_DECODE_MAX 10 /* Maximum decoders for Devices */ |