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author | Sia Jee Heng <jeeheng.sia@starfivetech.com> | 2024-01-28 18:14:40 -0800 |
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committer | Alistair Francis <alistair.francis@wdc.com> | 2024-03-08 15:40:08 +1000 |
commit | 3e6f1e61b4bc0facd13967580feed47d96a2c28c (patch) | |
tree | bc68a6635705095e4a1bb8f5f919c98a90c5df7e | |
parent | 7dd0b070fa09311a0330d0309c8cd9afeb081e79 (diff) | |
download | qemu-3e6f1e61b4bc0facd13967580feed47d96a2c28c.zip qemu-3e6f1e61b4bc0facd13967580feed47d96a2c28c.tar.gz qemu-3e6f1e61b4bc0facd13967580feed47d96a2c28c.tar.bz2 |
hw/riscv/virt-acpi-build.c: Generate SPCR table
Generate Serial Port Console Redirection Table (SPCR) for RISC-V
virtual machine.
Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240129021440.17640-3-jeeheng.sia@starfivetech.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
-rw-r--r-- | hw/riscv/virt-acpi-build.c | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c index fb8baf6..0baa902 100644 --- a/hw/riscv/virt-acpi-build.c +++ b/hw/riscv/virt-acpi-build.c @@ -174,6 +174,42 @@ acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap, aml_append(scope, dev); } +/* + * Serial Port Console Redirection Table (SPCR) + * Rev: 1.07 + */ + +static void +spcr_setup(GArray *table_data, BIOSLinker *linker, RISCVVirtState *s) +{ + AcpiSpcrData serial = { + .interface_type = 0, /* 16550 compatible */ + .base_addr.id = AML_AS_SYSTEM_MEMORY, + .base_addr.width = 32, + .base_addr.offset = 0, + .base_addr.size = 1, + .base_addr.addr = s->memmap[VIRT_UART0].base, + .interrupt_type = (1 << 4),/* Bit[4] RISC-V PLIC/APLIC */ + .pc_interrupt = 0, + .interrupt = UART0_IRQ, + .baud_rate = 7, /* 15200 */ + .parity = 0, + .stop_bits = 1, + .flow_control = 0, + .terminal_type = 3, /* ANSI */ + .language = 0, /* Language */ + .pci_device_id = 0xffff, /* not a PCI device*/ + .pci_vendor_id = 0xffff, /* not a PCI device*/ + .pci_bus = 0, + .pci_device = 0, + .pci_function = 0, + .pci_flags = 0, + .pci_segment = 0, + }; + + build_spcr(table_data, linker, &serial, 2, s->oem_id, s->oem_table_id); +} + /* RHCT Node[N] starts at offset 56 */ #define RHCT_NODE_ARRAY_OFFSET 56 @@ -556,6 +592,9 @@ static void virt_acpi_build(RISCVVirtState *s, AcpiBuildTables *tables) build_rhct(tables_blob, tables->linker, s); acpi_add_table(table_offsets, tables_blob); + spcr_setup(tables_blob, tables->linker, s); + + acpi_add_table(table_offsets, tables_blob); { AcpiMcfgInfo mcfg = { .base = s->memmap[VIRT_PCIE_MMIO].base, |