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| author | bellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162> | 2004-01-24 15:19:09 +0000 |
|---|---|---|
| committer | bellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162> | 2004-01-24 15:19:09 +0000 |
| commit | 3cf1e035ba16423d1278ac34bea2ec795a9716a3 (patch) | |
| tree | 379f8412034416eb5d872e228ad1e595d501bff6 | |
| parent | a6b025d37d13fffe6f2bc0b5fc8d88503348eeb7 (diff) | |
| download | qemu-3cf1e035ba16423d1278ac34bea2ec795a9716a3.zip qemu-3cf1e035ba16423d1278ac34bea2ec795a9716a3.tar.gz qemu-3cf1e035ba16423d1278ac34bea2ec795a9716a3.tar.bz2 | |
added TARGET_LONG_BITS
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@580 c046a42c-6fe2-441c-8c8c-71466251a162
| -rw-r--r-- | target-arm/cpu.h | 2 | ||||
| -rw-r--r-- | target-i386/cpu.h | 2 | ||||
| -rw-r--r-- | target-ppc/cpu.h | 2 | ||||
| -rw-r--r-- | target-sparc/cpu.h | 4 |
4 files changed, 8 insertions, 2 deletions
diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 7f755a7..174f60d 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -20,6 +20,8 @@ #ifndef CPU_ARM_H #define CPU_ARM_H +#define TARGET_LONG_BITS 32 + #include "cpu-defs.h" #define EXCP_UDEF 1 /* undefined instruction */ diff --git a/target-i386/cpu.h b/target-i386/cpu.h index 6be987c..a93486c 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -20,6 +20,8 @@ #ifndef CPU_I386_H #define CPU_I386_H +#define TARGET_LONG_BITS 32 + #include "cpu-defs.h" #define R_EAX 0 diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 850a88b..3809f20 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -23,6 +23,8 @@ #include <endian.h> #include <asm/byteorder.h> +#define TARGET_LONG_BITS 32 + #include "cpu-defs.h" //#define USE_OPEN_FIRMWARE diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h index 67fece7..af5ecb5 100644 --- a/target-sparc/cpu.h +++ b/target-sparc/cpu.h @@ -1,8 +1,8 @@ #ifndef CPU_SPARC_H #define CPU_SPARC_H -#include <setjmp.h> -#include "config.h" +#define TARGET_LONG_BITS 32 + #include "cpu-defs.h" /*#define EXCP_INTERRUPT 0x100*/ |