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| author | Jim Shu <jim.shu@sifive.com> | 2025-05-19 22:35:17 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2025-07-04 21:09:48 +1000 |
| commit | 3cb2edae740121cf5da3a9adb8190051e866eb01 (patch) | |
| tree | aa65657fa0cd0e933e8d4e96aa821d41977d084b | |
| parent | af27fc569af58e10d9e77afd10079809f05827bc (diff) | |
| download | qemu-3cb2edae740121cf5da3a9adb8190051e866eb01.zip qemu-3cb2edae740121cf5da3a9adb8190051e866eb01.tar.gz qemu-3cb2edae740121cf5da3a9adb8190051e866eb01.tar.bz2 | |
target/riscv: Fix VSTIP bit in sstc extension.
VSTIP is only writable when both [mh]envcfg.STCE is enabled, or it will
revert it's defined behavior as if sstc extension is not implemented.
Signed-off-by: Jim Shu <jim.shu@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20250519143518.11086-4-jim.shu@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| -rw-r--r-- | target/riscv/csr.c | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/target/riscv/csr.c b/target/riscv/csr.c index fb14972..d810294 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -3651,7 +3651,14 @@ static RISCVException rmw_mip64(CPURISCVState *env, int csrno, if (riscv_cpu_cfg(env)->ext_sstc && (env->priv == PRV_M) && get_field(env->menvcfg, MENVCFG_STCE)) { /* sstc extension forbids STIP & VSTIP to be writeable in mip */ - mask = mask & ~(MIP_STIP | MIP_VSTIP); + + /* STIP is not writable when menvcfg.STCE is enabled. */ + mask = mask & ~MIP_STIP; + + /* VSTIP is not writable when both [mh]envcfg.STCE are enabled. */ + if (get_field(env->henvcfg, HENVCFG_STCE)) { + mask = mask & ~MIP_VSTIP; + } } if (mask) { |