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| author | Jiaxun Yang <jiaxun.yang@flygoat.com> | 2022-10-24 15:35:40 +0100 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <philmd@linaro.org> | 2022-10-31 11:32:07 +0100 |
| commit | 3c43fc333be7747a29405bdf6b3bd9e82fa22164 (patch) | |
| tree | bbfaa01111022cfdaed055ab1c5d44961e34213f | |
| parent | d240d3fb14031ed2b00b86ab8e9082ba6bebce4d (diff) | |
| download | qemu-3c43fc333be7747a29405bdf6b3bd9e82fa22164.zip qemu-3c43fc333be7747a29405bdf6b3bd9e82fa22164.tar.gz qemu-3c43fc333be7747a29405bdf6b3bd9e82fa22164.tar.bz2 | |
hw/mips/boston: Don't set link_up for xilinx-pcie
PCIe port 0 and 1 had link_up set as false previously,
that makes those two ports effectively useless. It can
be annoying for users to find that the device they plug
on those buses won't work at all.
As link_up is true by default, just don't set it again in
boston platform code.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20221024143540.97545-1-jiaxun.yang@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
| -rw-r--r-- | hw/mips/boston.c | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/hw/mips/boston.c b/hw/mips/boston.c index cab63f4..2333bb6 100644 --- a/hw/mips/boston.c +++ b/hw/mips/boston.c @@ -425,7 +425,7 @@ static inline XilinxPCIEHost * xilinx_pcie_init(MemoryRegion *sys_mem, uint32_t bus_nr, hwaddr cfg_base, uint64_t cfg_size, hwaddr mmio_base, uint64_t mmio_size, - qemu_irq irq, bool link_up) + qemu_irq irq) { DeviceState *dev; MemoryRegion *cfg, *mmio; @@ -437,7 +437,6 @@ xilinx_pcie_init(MemoryRegion *sys_mem, uint32_t bus_nr, qdev_prop_set_uint64(dev, "cfg_size", cfg_size); qdev_prop_set_uint64(dev, "mmio_base", mmio_base); qdev_prop_set_uint64(dev, "mmio_size", mmio_size); - qdev_prop_set_bit(dev, "link_up", link_up); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); @@ -730,21 +729,21 @@ static void boston_mach_init(MachineState *machine) boston_memmap[BOSTON_PCIE0].size, boston_memmap[BOSTON_PCIE0_MMIO].base, boston_memmap[BOSTON_PCIE0_MMIO].size, - get_cps_irq(&s->cps, 2), false); + get_cps_irq(&s->cps, 2)); xilinx_pcie_init(sys_mem, 1, boston_memmap[BOSTON_PCIE1].base, boston_memmap[BOSTON_PCIE1].size, boston_memmap[BOSTON_PCIE1_MMIO].base, boston_memmap[BOSTON_PCIE1_MMIO].size, - get_cps_irq(&s->cps, 1), false); + get_cps_irq(&s->cps, 1)); pcie2 = xilinx_pcie_init(sys_mem, 2, boston_memmap[BOSTON_PCIE2].base, boston_memmap[BOSTON_PCIE2].size, boston_memmap[BOSTON_PCIE2_MMIO].base, boston_memmap[BOSTON_PCIE2_MMIO].size, - get_cps_irq(&s->cps, 0), true); + get_cps_irq(&s->cps, 0)); platreg = g_new(MemoryRegion, 1); memory_region_init_io(platreg, NULL, &boston_platreg_ops, s, |