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authorClément Chigot <chigot@adacore.com>2022-09-14 12:50:59 +0200
committerPeter Maydell <peter.maydell@linaro.org>2022-09-22 16:38:27 +0100
commit3a661024cc680104ce2cd21f8f5466dacba6f405 (patch)
tree454c168b70fc1c4388183f9c6a286194dee0a1c1
parentfb96d131eec66ecb2993c544058a8cb2c9c3521f (diff)
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target/arm: Fix alignment for VLD4.32
When requested, the alignment for VLD4.32 is 8 and not 16. See ARM documentation about VLD4 encoding: ebytes = 1 << UInt(size); if size == '10' then alignment = if a == '0' then 1 else 8; else alignment = if a == '0' then 1 else 4*ebytes; Signed-off-by: Clément Chigot <chigot@adacore.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220914105058.2787404-1-chigot@adacore.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-rw-r--r--target/arm/translate-neon.c6
1 files changed, 5 insertions, 1 deletions
diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c
index 321c17e..4016339 100644
--- a/target/arm/translate-neon.c
+++ b/target/arm/translate-neon.c
@@ -584,7 +584,11 @@ static bool trans_VLD_all_lanes(DisasContext *s, arg_VLD_all_lanes *a)
case 3:
return false;
case 4:
- align = pow2_align(size + 2);
+ if (size == 2) {
+ align = pow2_align(3);
+ } else {
+ align = pow2_align(size + 2);
+ }
break;
default:
g_assert_not_reached();