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author | Daniel Henrique Barboza <dbarboza@ventanamicro.com> | 2024-01-22 13:10:56 -0300 |
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committer | Alistair Francis <alistair.francis@wdc.com> | 2024-02-09 20:43:14 +1000 |
commit | 39b5efa5b8fd60f80101cb0f04447a4679097096 (patch) | |
tree | be700cb3de267865cdf925861bade7032b319e31 | |
parent | 04eb30a03cfc4195161996746d18a715457e0b42 (diff) | |
download | qemu-39b5efa5b8fd60f80101cb0f04447a4679097096.zip qemu-39b5efa5b8fd60f80101cb0f04447a4679097096.tar.gz qemu-39b5efa5b8fd60f80101cb0f04447a4679097096.tar.bz2 |
target/riscv/csr.c: use 'vlenb' instead of 'vlen'
As a bonus, we're being more idiomatic using cpu->cfg.vlenb when
reading CSR_VLENB.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240122161107.26737-3-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
-rw-r--r-- | target/riscv/csr.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target/riscv/csr.c b/target/riscv/csr.c index d666620..d9a0103 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -683,7 +683,7 @@ static RISCVException read_vl(CPURISCVState *env, int csrno, static int read_vlenb(CPURISCVState *env, int csrno, target_ulong *val) { - *val = riscv_cpu_cfg(env)->vlen >> 3; + *val = riscv_cpu_cfg(env)->vlenb; return RISCV_EXCP_NONE; } @@ -738,7 +738,7 @@ static RISCVException write_vstart(CPURISCVState *env, int csrno, * The vstart CSR is defined to have only enough writable bits * to hold the largest element index, i.e. lg2(VLEN) bits. */ - env->vstart = val & ~(~0ULL << ctzl(riscv_cpu_cfg(env)->vlen)); + env->vstart = val & ~(~0ULL << ctzl(riscv_cpu_cfg(env)->vlenb << 3)); return RISCV_EXCP_NONE; } |