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| author | Richard Henderson <richard.henderson@linaro.org> | 2025-05-04 09:59:29 -0700 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2025-05-28 08:08:48 +0100 |
| commit | 396c12d00e3944e79159c9f3cb934f26f32ef861 (patch) | |
| tree | 64b22cdeda4dcef69461c5ee169ec9de2245843b | |
| parent | 353f703cf1959228affc23b5bba8a18738736cf4 (diff) | |
| download | qemu-396c12d00e3944e79159c9f3cb934f26f32ef861.zip qemu-396c12d00e3944e79159c9f3cb934f26f32ef861.tar.gz qemu-396c12d00e3944e79159c9f3cb934f26f32ef861.tar.bz2 | |
target/mips: Fill in TCGCPUOps.pointer_wrap
Check 32 vs 64-bit addressing state.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| -rw-r--r-- | target/mips/cpu.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 4cbfb94..1f6c41f 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -560,6 +560,14 @@ static TCGTBCPUState mips_get_tb_cpu_state(CPUState *cs) }; } +#ifndef CONFIG_USER_ONLY +static vaddr mips_pointer_wrap(CPUState *cs, int mmu_idx, + vaddr result, vaddr base) +{ + return cpu_env(cs)->hflags & MIPS_HFLAG_AWRAP ? (int32_t)result : result; +} +#endif + static const TCGCPUOps mips_tcg_ops = { .mttcg_supported = TARGET_LONG_BITS == 32, .guest_default_memory_order = 0, @@ -573,6 +581,7 @@ static const TCGCPUOps mips_tcg_ops = { #if !defined(CONFIG_USER_ONLY) .tlb_fill = mips_cpu_tlb_fill, + .pointer_wrap = mips_pointer_wrap, .cpu_exec_interrupt = mips_cpu_exec_interrupt, .cpu_exec_halt = mips_cpu_has_work, .cpu_exec_reset = cpu_reset, |