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author | Peter Maydell <peter.maydell@linaro.org> | 2025-01-24 16:27:38 +0000 |
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committer | Peter Maydell <peter.maydell@linaro.org> | 2025-01-28 18:40:19 +0000 |
commit | 3847b5b1fbb2d6d4ab1dffd8842ffc3d0c3ddb37 (patch) | |
tree | 37d193227b46870c510e11eb69c694fdf5288b0c | |
parent | 230c2bd3f2882e007abc80d513b86770adb7b0e5 (diff) | |
download | qemu-3847b5b1fbb2d6d4ab1dffd8842ffc3d0c3ddb37.zip qemu-3847b5b1fbb2d6d4ab1dffd8842ffc3d0c3ddb37.tar.gz qemu-3847b5b1fbb2d6d4ab1dffd8842ffc3d0c3ddb37.tar.bz2 |
target/arm: Remove now-unused vfp.fp_status_f16 and FPST_FPCR_F16
Now we have moved all the uses of vfp.fp_status_f16 and FPST_FPCR_F16
to the new A32 or A64 fields, we can remove these.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250124162836.2332150-19-peter.maydell@linaro.org
-rw-r--r-- | target/arm/cpu.c | 1 | ||||
-rw-r--r-- | target/arm/cpu.h | 2 | ||||
-rw-r--r-- | target/arm/tcg/translate.h | 6 | ||||
-rw-r--r-- | target/arm/vfp_helper.c | 7 |
4 files changed, 0 insertions, 16 deletions
diff --git a/target/arm/cpu.c b/target/arm/cpu.c index ff8514e..7a83b9e 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -575,7 +575,6 @@ static void arm_cpu_reset_hold(Object *obj, ResetType type) arm_set_default_fp_behaviours(&env->vfp.fp_status_a32); arm_set_default_fp_behaviours(&env->vfp.fp_status_a64); arm_set_default_fp_behaviours(&env->vfp.standard_fp_status); - arm_set_default_fp_behaviours(&env->vfp.fp_status_f16); arm_set_default_fp_behaviours(&env->vfp.fp_status_f16_a32); arm_set_default_fp_behaviours(&env->vfp.fp_status_f16_a64); arm_set_default_fp_behaviours(&env->vfp.standard_fp_status_f16); diff --git a/target/arm/cpu.h b/target/arm/cpu.h index be409c5..2213c27 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -635,7 +635,6 @@ typedef struct CPUArchState { * * fp_status_a32: is the "normal" fp status for AArch32 insns * fp_status_a64: is the "normal" fp status for AArch64 insns - * fp_status_fp16: used for half-precision calculations * fp_status_fp16_a32: used for AArch32 half-precision calculations * fp_status_fp16_a64: used for AArch64 half-precision calculations * standard_fp_status : the ARM "Standard FPSCR Value" @@ -663,7 +662,6 @@ typedef struct CPUArchState { */ float_status fp_status_a32; float_status fp_status_a64; - float_status fp_status_f16; float_status fp_status_f16_a32; float_status fp_status_f16_a64; float_status standard_fp_status; diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h index d84c6d7..084ee63 100644 --- a/target/arm/tcg/translate.h +++ b/target/arm/tcg/translate.h @@ -672,7 +672,6 @@ static inline CPUARMTBFlags arm_tbflags_from_tb(const TranslationBlock *tb) typedef enum ARMFPStatusFlavour { FPST_A32, FPST_A64, - FPST_FPCR_F16, FPST_A32_F16, FPST_A64_F16, FPST_STD, @@ -691,8 +690,6 @@ typedef enum ARMFPStatusFlavour { * for AArch32 non-FP16 operations controlled by the FPCR * FPST_A64 * for AArch64 non-FP16 operations controlled by the FPCR - * FPST_FPCR_F16 - * for operations controlled by the FPCR where FPCR.FZ16 is to be used * FPST_A32_F16 * for AArch32 operations controlled by the FPCR where FPCR.FZ16 is to be used * FPST_A64_F16 @@ -714,9 +711,6 @@ static inline TCGv_ptr fpstatus_ptr(ARMFPStatusFlavour flavour) case FPST_A64: offset = offsetof(CPUARMState, vfp.fp_status_a64); break; - case FPST_FPCR_F16: - offset = offsetof(CPUARMState, vfp.fp_status_f16); - break; case FPST_A32_F16: offset = offsetof(CPUARMState, vfp.fp_status_f16_a32); break; diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c index f3aa80b..3ed69d7 100644 --- a/target/arm/vfp_helper.c +++ b/target/arm/vfp_helper.c @@ -67,8 +67,6 @@ static uint32_t vfp_get_fpsr_from_host(CPUARMState *env) i |= get_float_exception_flags(&env->vfp.fp_status_a64); i |= get_float_exception_flags(&env->vfp.standard_fp_status); /* FZ16 does not generate an input denormal exception. */ - i |= (get_float_exception_flags(&env->vfp.fp_status_f16) - & ~float_flag_input_denormal); i |= (get_float_exception_flags(&env->vfp.fp_status_f16_a32) & ~float_flag_input_denormal); i |= (get_float_exception_flags(&env->vfp.fp_status_f16_a64) @@ -87,7 +85,6 @@ static void vfp_clear_float_status_exc_flags(CPUARMState *env) */ set_float_exception_flags(0, &env->vfp.fp_status_a32); set_float_exception_flags(0, &env->vfp.fp_status_a64); - set_float_exception_flags(0, &env->vfp.fp_status_f16); set_float_exception_flags(0, &env->vfp.fp_status_f16_a32); set_float_exception_flags(0, &env->vfp.fp_status_f16_a64); set_float_exception_flags(0, &env->vfp.standard_fp_status); @@ -118,17 +115,14 @@ static void vfp_set_fpcr_to_host(CPUARMState *env, uint32_t val, uint32_t mask) } set_float_rounding_mode(i, &env->vfp.fp_status_a32); set_float_rounding_mode(i, &env->vfp.fp_status_a64); - set_float_rounding_mode(i, &env->vfp.fp_status_f16); set_float_rounding_mode(i, &env->vfp.fp_status_f16_a32); set_float_rounding_mode(i, &env->vfp.fp_status_f16_a64); } if (changed & FPCR_FZ16) { bool ftz_enabled = val & FPCR_FZ16; - set_flush_to_zero(ftz_enabled, &env->vfp.fp_status_f16); set_flush_to_zero(ftz_enabled, &env->vfp.fp_status_f16_a32); set_flush_to_zero(ftz_enabled, &env->vfp.fp_status_f16_a64); set_flush_to_zero(ftz_enabled, &env->vfp.standard_fp_status_f16); - set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status_f16); set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status_f16_a32); set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status_f16_a64); set_flush_inputs_to_zero(ftz_enabled, &env->vfp.standard_fp_status_f16); @@ -144,7 +138,6 @@ static void vfp_set_fpcr_to_host(CPUARMState *env, uint32_t val, uint32_t mask) bool dnan_enabled = val & FPCR_DN; set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_a32); set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_a64); - set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_f16); set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_f16_a32); set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_f16_a64); } |