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author | Alistair Francis <alistair.francis@wdc.com> | 2020-01-31 17:01:59 -0800 |
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committer | Palmer Dabbelt <palmerdabbelt@google.com> | 2020-02-27 13:45:31 -0800 |
commit | 35f690391bd69922a1987d44546b884adaf29a57 (patch) | |
tree | e7d1308b25af3e79d9ef9ac2779a37f114181b02 | |
parent | 0a42f4c4408824dc7cb9ff60c9bdce6dcc0d24a5 (diff) | |
download | qemu-35f690391bd69922a1987d44546b884adaf29a57.zip qemu-35f690391bd69922a1987d44546b884adaf29a57.tar.gz qemu-35f690391bd69922a1987d44546b884adaf29a57.tar.bz2 |
target/riscv: Print priv and virt in disas log
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
-rw-r--r-- | target/riscv/translate.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/target/riscv/translate.c b/target/riscv/translate.c index d5de7f4..eff064d 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -810,7 +810,15 @@ static void riscv_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) static void riscv_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu) { +#ifndef CONFIG_USER_ONLY + RISCVCPU *rvcpu = RISCV_CPU(cpu); + CPURISCVState *env = &rvcpu->env; +#endif + qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); +#ifndef CONFIG_USER_ONLY + qemu_log("Priv: "TARGET_FMT_ld"; Virt: "TARGET_FMT_ld"\n", env->priv, env->virt); +#endif log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size); } |