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author | Peter Maydell <peter.maydell@linaro.org> | 2023-08-31 09:45:17 +0100 |
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committer | Peter Maydell <peter.maydell@linaro.org> | 2023-08-31 09:45:17 +0100 |
commit | 35aa6715ddcd9748bae5bc01563331e8eae8d7cf (patch) | |
tree | 1939765a951a292aba691ad0afccd1946c290331 | |
parent | 12517bc978e62ce19df0160ad2ef229169a567b2 (diff) | |
download | qemu-35aa6715ddcd9748bae5bc01563331e8eae8d7cf.zip qemu-35aa6715ddcd9748bae5bc01563331e8eae8d7cf.tar.gz qemu-35aa6715ddcd9748bae5bc01563331e8eae8d7cf.tar.bz2 |
target/arm: Catch illegal-exception-return from EL3 with bad NSE/NS
The architecture requires (R_TYTWB) that an attempt to return from EL3
when SCR_EL3.{NSE,NS} are {1,0} is an illegal exception return. (This
enforces that the CPU can't ever be executing below EL3 with the
NSE,NS bits indicating an invalid security state.)
We were missing this check; add it.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230807150618.101357-1-peter.maydell@linaro.org
-rw-r--r-- | target/arm/tcg/helper-a64.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c index 1c9370f..0cf56f6 100644 --- a/target/arm/tcg/helper-a64.c +++ b/target/arm/tcg/helper-a64.c @@ -780,6 +780,15 @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc) spsr &= ~PSTATE_SS; } + /* + * FEAT_RME forbids return from EL3 with an invalid security state. + * We don't need an explicit check for FEAT_RME here because we enforce + * in scr_write() that you can't set the NSE bit without it. + */ + if (cur_el == 3 && (env->cp15.scr_el3 & (SCR_NS | SCR_NSE)) == SCR_NSE) { + goto illegal_return; + } + new_el = el_from_spsr(spsr); if (new_el == -1) { goto illegal_return; |