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authorJiajie Chen <c@jia.je>2023-08-22 09:13:51 +0200
committerSong Gao <gaosong@loongson.cn>2023-08-24 11:17:57 +0800
commit34423c01941928974f4854bc23a949789154fee7 (patch)
tree9709e15a492c6d1298247d156c24524cce444fd8
parent3966582099b0c94b45a2ea0fd8afb0dcac8ad292 (diff)
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target/loongarch: Extract make_address_x() helper
Signed-off-by: Jiajie Chen <c@jia.je> Co-authored-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20230822032724.1353391-6-gaosong@loongson.cn> [PMD: Extract helper from bigger patch] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230822071405.35386-6-philmd@linaro.org>
-rw-r--r--target/loongarch/insn_trans/trans_fmemory.c.inc18
-rw-r--r--target/loongarch/insn_trans/trans_lsx.c.inc6
-rw-r--r--target/loongarch/insn_trans/trans_memory.c.inc6
-rw-r--r--target/loongarch/translate.c12
4 files changed, 22 insertions, 20 deletions
diff --git a/target/loongarch/insn_trans/trans_fmemory.c.inc b/target/loongarch/insn_trans/trans_fmemory.c.inc
index 91c09fb..88ad209 100644
--- a/target/loongarch/insn_trans/trans_fmemory.c.inc
+++ b/target/loongarch/insn_trans/trans_fmemory.c.inc
@@ -57,8 +57,7 @@ static bool gen_floadx(DisasContext *ctx, arg_frr *a, MemOp mop)
CHECK_FPE;
- addr = tcg_temp_new();
- tcg_gen_add_tl(addr, src1, src2);
+ addr = make_address_x(ctx, src1, src2);
tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, mop);
maybe_nanbox_load(dest, mop);
set_fpr(a->fd, dest);
@@ -75,8 +74,7 @@ static bool gen_fstorex(DisasContext *ctx, arg_frr *a, MemOp mop)
CHECK_FPE;
- addr = tcg_temp_new();
- tcg_gen_add_tl(addr, src1, src2);
+ addr = make_address_x(ctx, src1, src2);
tcg_gen_qemu_st_tl(src3, addr, ctx->mem_idx, mop);
return true;
@@ -91,9 +89,8 @@ static bool gen_fload_gt(DisasContext *ctx, arg_frr *a, MemOp mop)
CHECK_FPE;
- addr = tcg_temp_new();
gen_helper_asrtgt_d(cpu_env, src1, src2);
- tcg_gen_add_tl(addr, src1, src2);
+ addr = make_address_x(ctx, src1, src2);
tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, mop);
maybe_nanbox_load(dest, mop);
set_fpr(a->fd, dest);
@@ -110,9 +107,8 @@ static bool gen_fstore_gt(DisasContext *ctx, arg_frr *a, MemOp mop)
CHECK_FPE;
- addr = tcg_temp_new();
gen_helper_asrtgt_d(cpu_env, src1, src2);
- tcg_gen_add_tl(addr, src1, src2);
+ addr = make_address_x(ctx, src1, src2);
tcg_gen_qemu_st_tl(src3, addr, ctx->mem_idx, mop);
return true;
@@ -127,9 +123,8 @@ static bool gen_fload_le(DisasContext *ctx, arg_frr *a, MemOp mop)
CHECK_FPE;
- addr = tcg_temp_new();
gen_helper_asrtle_d(cpu_env, src1, src2);
- tcg_gen_add_tl(addr, src1, src2);
+ addr = make_address_x(ctx, src1, src2);
tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, mop);
maybe_nanbox_load(dest, mop);
set_fpr(a->fd, dest);
@@ -146,9 +141,8 @@ static bool gen_fstore_le(DisasContext *ctx, arg_frr *a, MemOp mop)
CHECK_FPE;
- addr = tcg_temp_new();
gen_helper_asrtle_d(cpu_env, src1, src2);
- tcg_gen_add_tl(addr, src1, src2);
+ addr = make_address_x(ctx, src1, src2);
tcg_gen_qemu_st_tl(src3, addr, ctx->mem_idx, mop);
return true;
diff --git a/target/loongarch/insn_trans/trans_lsx.c.inc b/target/loongarch/insn_trans/trans_lsx.c.inc
index 68779da..875cb7d 100644
--- a/target/loongarch/insn_trans/trans_lsx.c.inc
+++ b/target/loongarch/insn_trans/trans_lsx.c.inc
@@ -4315,14 +4315,13 @@ static bool trans_vldx(DisasContext *ctx, arg_vrr *a)
CHECK_SXE;
- addr = tcg_temp_new();
src1 = gpr_src(ctx, a->rj, EXT_NONE);
src2 = gpr_src(ctx, a->rk, EXT_NONE);
val = tcg_temp_new_i128();
rl = tcg_temp_new_i64();
rh = tcg_temp_new_i64();
- tcg_gen_add_tl(addr, src1, src2);
+ addr = make_address_x(ctx, src1, src2);
tcg_gen_qemu_ld_i128(val, addr, ctx->mem_idx, MO_128 | MO_TE);
tcg_gen_extr_i128_i64(rl, rh, val);
set_vreg64(rh, a->vd, 1);
@@ -4339,14 +4338,13 @@ static bool trans_vstx(DisasContext *ctx, arg_vrr *a)
CHECK_SXE;
- addr = tcg_temp_new();
src1 = gpr_src(ctx, a->rj, EXT_NONE);
src2 = gpr_src(ctx, a->rk, EXT_NONE);
val = tcg_temp_new_i128();
ah = tcg_temp_new_i64();
al = tcg_temp_new_i64();
- tcg_gen_add_tl(addr, src1, src2);
+ addr = make_address_x(ctx, src1, src2);
get_vreg64(ah, a->vd, 1);
get_vreg64(al, a->vd, 0);
tcg_gen_concat_i64_i128(val, al, ah);
diff --git a/target/loongarch/insn_trans/trans_memory.c.inc b/target/loongarch/insn_trans/trans_memory.c.inc
index 75cfdf5..ccebd0a 100644
--- a/target/loongarch/insn_trans/trans_memory.c.inc
+++ b/target/loongarch/insn_trans/trans_memory.c.inc
@@ -39,9 +39,8 @@ static bool gen_loadx(DisasContext *ctx, arg_rrr *a, MemOp mop)
TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
- TCGv addr = tcg_temp_new();
+ TCGv addr = make_address_x(ctx, src1, src2);
- tcg_gen_add_tl(addr, src1, src2);
tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, mop);
gen_set_gpr(a->rd, dest, EXT_NONE);
@@ -53,9 +52,8 @@ static bool gen_storex(DisasContext *ctx, arg_rrr *a, MemOp mop)
TCGv data = gpr_src(ctx, a->rd, EXT_NONE);
TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
- TCGv addr = tcg_temp_new();
+ TCGv addr = make_address_x(ctx, src1, src2);
- tcg_gen_add_tl(addr, src1, src2);
tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, mop);
return true;
diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c
index ac84774..a68a979 100644
--- a/target/loongarch/translate.c
+++ b/target/loongarch/translate.c
@@ -208,6 +208,18 @@ static void set_fpr(int reg_num, TCGv val)
offsetof(CPULoongArchState, fpr[reg_num].vreg.D(0)));
}
+static TCGv make_address_x(DisasContext *ctx, TCGv base, TCGv addend)
+{
+ TCGv temp = NULL;
+
+ if (addend) {
+ temp = tcg_temp_new();
+ tcg_gen_add_tl(temp, base, addend);
+ base = temp;
+ }
+ return base;
+}
+
#include "decode-insns.c.inc"
#include "insn_trans/trans_arith.c.inc"
#include "insn_trans/trans_shift.c.inc"