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author | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-05-31 16:18:58 +0000 |
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committer | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-05-31 16:18:58 +0000 |
commit | 33ac7f1630d8655b92b6a53d59886fca2b64da10 (patch) | |
tree | d71acd478ba2fa4a2e51bb88d45e03b9012a3b4d | |
parent | 924b2c07cdfaba9ac408fc5fa77da75a570f9dc5 (diff) | |
download | qemu-33ac7f1630d8655b92b6a53d59886fca2b64da10.zip qemu-33ac7f1630d8655b92b6a53d59886fca2b64da10.tar.gz qemu-33ac7f1630d8655b92b6a53d59886fca2b64da10.tar.bz2 |
Don't kill the registered irqs on reset.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2903 c046a42c-6fe2-441c-8c8c-71466251a162
-rw-r--r-- | target-mips/cpu.h | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/target-mips/cpu.h b/target-mips/cpu.h index 9fa0ca8..6dff8ef 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -284,10 +284,8 @@ struct CPUMIPSState { int CCRes; /* Cycle count resolution/divisor */ int Status_rw_bitmask; /* Read/write bits in CP0_Status */ -#if defined(CONFIG_USER_ONLY) +#ifdef CONFIG_USER_ONLY target_ulong tls_value; -#else - void *irq[8]; #endif CPU_COMMON @@ -298,6 +296,9 @@ struct CPUMIPSState { const char *initrd_filename; mips_def_t *cpu_model; +#ifndef CONFIG_USER_ONLY + void *irq[8]; +#endif struct QEMUTimer *timer; /* Internal timer */ }; |