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| author | Xu Lu <luxu.kernel@bytedance.com> | 2025-07-08 14:07:20 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2025-07-30 10:59:26 +1000 |
| commit | 30ef718423e8018723087cd17be0fd9c6dfa2e53 (patch) | |
| tree | 914fc06890a53c4a993e2aac8529b9cad932b261 | |
| parent | 09ac27a9b59bf87786cb35f7126fb5788b0b4bca (diff) | |
| download | qemu-30ef718423e8018723087cd17be0fd9c6dfa2e53.zip qemu-30ef718423e8018723087cd17be0fd9c6dfa2e53.tar.gz qemu-30ef718423e8018723087cd17be0fd9c6dfa2e53.tar.bz2 | |
target/riscv: Fix exception type when VU accesses supervisor CSRs
When supervisor CSRs are accessed from VU-mode, a virtual instruction
exception should be raised instead of an illegal instruction.
Fixes: c1fbcecb3a (target/riscv: Fix csr number based privilege checking)
Signed-off-by: Xu Lu <luxu.kernel@bytedance.com>
Reviewed-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Nutty Liu <liujingqi@lanxincomputing.com>
Message-ID: <20250708060720.7030-1-luxu.kernel@bytedance.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| -rw-r--r-- | target/riscv/csr.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 8631be9..9bebfae 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -5577,7 +5577,7 @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env, csr_priv = get_field(csrno, 0x300); if (!env->debugger && (effective_priv < csr_priv)) { - if (csr_priv == (PRV_S + 1) && env->virt_enabled) { + if (csr_priv <= (PRV_S + 1) && env->virt_enabled) { return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; } return RISCV_EXCP_ILLEGAL_INST; |