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| author | Clément Mathieu--Drif <clement.mathieu--drif@eviden.com> | 2024-12-12 16:37:44 +0800 |
|---|---|---|
| committer | Michael S. Tsirkin <mst@redhat.com> | 2025-01-15 13:06:14 -0500 |
| commit | 305e469b7188e5f1a896c40853d84fa158ee6ba4 (patch) | |
| tree | 31dead0e48990d5dd7e0c4a2599ffd759f551b01 | |
| parent | eb9da9d2632839c386ecbfc50f78032c9f3a75a4 (diff) | |
| download | qemu-305e469b7188e5f1a896c40853d84fa158ee6ba4.zip qemu-305e469b7188e5f1a896c40853d84fa158ee6ba4.tar.gz qemu-305e469b7188e5f1a896c40853d84fa158ee6ba4.tar.bz2 | |
intel_iommu: Check if the input address is canonical
Stage-1 translation must fail if the address to translate is
not canonical.
Signed-off-by: Clément Mathieu--Drif <clement.mathieu--drif@eviden.com>
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Reviewed-by: Yi Liu <yi.l.liu@intel.com>
Message-Id: <20241212083757.605022-8-zhenzhong.duan@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
| -rw-r--r-- | hw/i386/intel_iommu.c | 23 | ||||
| -rw-r--r-- | hw/i386/intel_iommu_internal.h | 1 |
2 files changed, 24 insertions, 0 deletions
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index bd6de71..3959fe4 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -1824,6 +1824,7 @@ static const bool vtd_qualified_faults[] = { [VTD_FR_FS_PAGING_ENTRY_P] = true, [VTD_FR_FS_PAGING_ENTRY_RSVD] = true, [VTD_FR_PASID_ENTRY_FSPTPTR_INV] = true, + [VTD_FR_FS_NON_CANONICAL] = true, [VTD_FR_FS_PAGING_ENTRY_US] = true, [VTD_FR_SM_WRITE] = true, [VTD_FR_SM_INTERRUPT_ADDR] = true, @@ -1930,6 +1931,22 @@ static inline bool vtd_flpte_present(uint64_t flpte) return !!(flpte & VTD_FL_P); } +/* Return true if IOVA is canonical, otherwise false. */ +static bool vtd_iova_fl_check_canonical(IntelIOMMUState *s, uint64_t iova, + VTDContextEntry *ce, uint32_t pasid) +{ + uint64_t iova_limit = vtd_iova_limit(s, ce, s->aw_bits, pasid); + uint64_t upper_bits_mask = ~(iova_limit - 1); + uint64_t upper_bits = iova & upper_bits_mask; + bool msb = ((iova & (iova_limit >> 1)) != 0); + + if (msb) { + return upper_bits == upper_bits_mask; + } else { + return !upper_bits; + } +} + /* * Given the @iova, get relevant @flptep. @flpte_level will be the last level * of the translation, can be used for deciding the size of large page. @@ -1945,6 +1962,12 @@ static int vtd_iova_to_flpte(IntelIOMMUState *s, VTDContextEntry *ce, uint32_t offset; uint64_t flpte; + if (!vtd_iova_fl_check_canonical(s, iova, ce, pasid)) { + error_report_once("%s: detected non canonical IOVA (iova=0x%" PRIx64 "," + "pasid=0x%" PRIx32 ")", __func__, iova, pasid); + return -VTD_FR_FS_NON_CANONICAL; + } + while (true) { offset = vtd_iova_level_offset(iova, level); flpte = vtd_get_pte(addr, offset); diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index 86d3354..3e7365d 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -326,6 +326,7 @@ typedef enum VTDFaultReason { /* Non-zero reserved field in present first-stage paging entry */ VTD_FR_FS_PAGING_ENTRY_RSVD = 0x72, VTD_FR_PASID_ENTRY_FSPTPTR_INV = 0x73, /* Invalid FSPTPTR in PASID entry */ + VTD_FR_FS_NON_CANONICAL = 0x80, /* SNG.1 : Address for FS not canonical.*/ VTD_FR_FS_PAGING_ENTRY_US = 0x81, /* Privilege violation */ VTD_FR_SM_WRITE = 0x85, /* No write permission */ |