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| author | Heinrich Schuchardt <heinrich.schuchardt@canonical.com> | 2023-10-30 12:21:05 +0200 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2023-11-07 11:06:02 +1000 |
| commit | 2f32dcabc2f0dfe7ee8c604dafb8ef450d78f452 (patch) | |
| tree | e3e1f25ed9a129abf3a20f227c0b6a532cc131ee | |
| parent | 672ec6061f13af21cbfa560ab2c0eea1a600d950 (diff) | |
| download | qemu-2f32dcabc2f0dfe7ee8c604dafb8ef450d78f452.zip qemu-2f32dcabc2f0dfe7ee8c604dafb8ef450d78f452.tar.gz qemu-2f32dcabc2f0dfe7ee8c604dafb8ef450d78f452.tar.bz2 | |
target/riscv: correct csr_ops[CSR_MSECCFG]
The CSR register mseccfg is used by multiple extensions: Smepm and Zkr.
Consider this when checking the existence of the register.
Fixes: 77442380ecbe ("target/riscv: rvk: add CSR support for Zkr")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231030102105.19501-1-heinrich.schuchardt@canonical.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| -rw-r--r-- | target/riscv/csr.c | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 4ca96dd..fc26b52 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -528,11 +528,14 @@ static RISCVException pmp(CPURISCVState *env, int csrno) return RISCV_EXCP_ILLEGAL_INST; } -static RISCVException smepmp(CPURISCVState *env, int csrno) +static RISCVException have_mseccfg(CPURISCVState *env, int csrno) { if (riscv_cpu_cfg(env)->ext_smepmp) { return RISCV_EXCP_NONE; } + if (riscv_cpu_cfg(env)->ext_zkr) { + return RISCV_EXCP_NONE; + } return RISCV_EXCP_ILLEGAL_INST; } @@ -4766,7 +4769,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { [CSR_VSIPH] = { "vsiph", aia_hmode32, NULL, NULL, rmw_vsiph }, /* Physical Memory Protection */ - [CSR_MSECCFG] = { "mseccfg", smepmp, read_mseccfg, write_mseccfg, + [CSR_MSECCFG] = { "mseccfg", have_mseccfg, read_mseccfg, write_mseccfg, .min_priv_ver = PRIV_VERSION_1_11_0 }, [CSR_PMPCFG0] = { "pmpcfg0", pmp, read_pmpcfg, write_pmpcfg }, [CSR_PMPCFG1] = { "pmpcfg1", pmp, read_pmpcfg, write_pmpcfg }, |