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| author | Michael Tokarev <mjt@tls.msk.ru> | 2025-05-07 20:03:14 +0300 |
|---|---|---|
| committer | Michael Tokarev <mjt@tls.msk.ru> | 2025-05-09 23:49:26 +0300 |
| commit | 2ddf5a8714221568dbdd8119ca123933cf5fad46 (patch) | |
| tree | fd8b513f171fa265cba8dddc924a38255080bc4a | |
| parent | c7c513389c6cb8c6dd60e55d1c99244de4e93663 (diff) | |
| download | qemu-2ddf5a8714221568dbdd8119ca123933cf5fad46.zip qemu-2ddf5a8714221568dbdd8119ca123933cf5fad46.tar.gz qemu-2ddf5a8714221568dbdd8119ca123933cf5fad46.tar.bz2 | |
qapi/qom.json: fix "the the" typo in comment
Suggested-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
| -rw-r--r-- | qapi/qom.json | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/qapi/qom.json b/qapi/qom.json index 28ce24c..04c118e 100644 --- a/qapi/qom.json +++ b/qapi/qom.json @@ -871,7 +871,7 @@ # link characteristics read from PCIe Configuration space. # To get the full path latency from CPU to CXL attached DRAM # CXL device: Add the latency from CPU to Generic Port (from -# HMAT indexed via the the node ID in this SRAT structure) to +# HMAT indexed via the node ID in this SRAT structure) to # that for CXL bus links, the latency across intermediate switches # and from the EP port to the actual memory. Bandwidth is more # complex as there may be interleaving across multiple devices |