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| author | Richard Henderson <richard.henderson@linaro.org> | 2023-10-25 21:14:00 -0700 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2023-11-06 08:27:21 -0800 |
| commit | 2cff741da81416ba7d4d8f2470e75d0e13bccae4 (patch) | |
| tree | 48f7af100c0b90febaa50d24e4914d12ba21315c | |
| parent | 42221a64da3ade66b01952a84307acc7061c1a05 (diff) | |
| download | qemu-2cff741da81416ba7d4d8f2470e75d0e13bccae4.zip qemu-2cff741da81416ba7d4d8f2470e75d0e13bccae4.tar.gz qemu-2cff741da81416ba7d4d8f2470e75d0e13bccae4.tar.bz2 | |
tcg/mips: Always implement movcond
Expand as branch over move if not supported in the ISA.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20231026041404.1229328-3-richard.henderson@linaro.org>
| -rw-r--r-- | tcg/mips/tcg-target.c.inc | 19 | ||||
| -rw-r--r-- | tcg/mips/tcg-target.h | 4 |
2 files changed, 16 insertions, 7 deletions
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 89681f0..82b078b 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -1070,13 +1070,22 @@ static void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGReg ret, if (v2 != 0) { tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP1); } - } else { - MIPSInsn m_opc = eqz ? OPC_MOVZ : OPC_MOVN; + return; + } - tcg_out_opc_reg(s, m_opc, ret, v1, c1); + /* This should be guaranteed via constraints */ + tcg_debug_assert(v2 == ret); - /* This should be guaranteed via constraints */ - tcg_debug_assert(v2 == ret); + if (use_movnz_instructions) { + MIPSInsn m_opc = eqz ? OPC_MOVZ : OPC_MOVN; + tcg_out_opc_reg(s, m_opc, ret, v1, c1); + } else { + /* Invert the condition in order to branch over the move. */ + MIPSInsn b_opc = eqz ? OPC_BNE : OPC_BEQ; + tcg_out_opc_imm(s, b_opc, c1, TCG_REG_ZERO, 2); + tcg_out_nop(s); + /* Open-code tcg_out_mov, without the nop-move check. */ + tcg_out_opc_reg(s, OPC_OR, ret, v1, TCG_REG_ZERO); } } diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index c0576f6..0a4083f 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -154,7 +154,7 @@ extern bool use_mips32r2_instructions; #endif /* optional instructions detected at runtime */ -#define TCG_TARGET_HAS_movcond_i32 use_movnz_instructions +#define TCG_TARGET_HAS_movcond_i32 1 #define TCG_TARGET_HAS_bswap16_i32 use_mips32r2_instructions #define TCG_TARGET_HAS_deposit_i32 use_mips32r2_instructions #define TCG_TARGET_HAS_extract_i32 use_mips32r2_instructions @@ -169,7 +169,7 @@ extern bool use_mips32r2_instructions; #define TCG_TARGET_HAS_qemu_st8_i32 0 #if TCG_TARGET_REG_BITS == 64 -#define TCG_TARGET_HAS_movcond_i64 use_movnz_instructions +#define TCG_TARGET_HAS_movcond_i64 1 #define TCG_TARGET_HAS_bswap16_i64 use_mips32r2_instructions #define TCG_TARGET_HAS_bswap32_i64 use_mips32r2_instructions #define TCG_TARGET_HAS_bswap64_i64 use_mips32r2_instructions |