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| author | Peter Crosthwaite <peter.crosthwaite@xilinx.com> | 2014-01-06 10:16:39 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2014-01-07 19:18:06 +0000 |
| commit | 2c628d98989fa224dc3c07033ba4d89562a9bb5f (patch) | |
| tree | 10712af9673866c6ff522d217497c97e7aa3e182 | |
| parent | a24234cad03d70612e30494f21062fcee5eb9f0e (diff) | |
| download | qemu-2c628d98989fa224dc3c07033ba4d89562a9bb5f.zip qemu-2c628d98989fa224dc3c07033ba4d89562a9bb5f.tar.gz qemu-2c628d98989fa224dc3c07033ba4d89562a9bb5f.tar.bz2 | |
char/cadence_uart: Define Missing SR/ISR fields
Some (interrupt) status register bits relating to the TxFIFO path were
not defined. Define them. This prepares support for proper Tx data path
flow control.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: 2068b963f0af8cc834c353944e9fa816d950b163.1388626249.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | hw/char/cadence_uart.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c index ddd7267..216eed7 100644 --- a/hw/char/cadence_uart.c +++ b/hw/char/cadence_uart.c @@ -34,6 +34,9 @@ #define UART_SR_INTR_RFUL 0x00000004 #define UART_SR_INTR_TEMPTY 0x00000008 #define UART_SR_INTR_TFUL 0x00000010 +/* somewhat awkwardly, TTRIG is misaligned between SR and ISR */ +#define UART_SR_TTRIG 0x00002000 +#define UART_INTR_TTRIG 0x00000400 /* bits fields in CSR that correlate to CISR. If any of these bits are set in * SR, then the same bit in CISR is set high too */ #define UART_SR_TO_CISR_MASK 0x0000001F @@ -43,6 +46,7 @@ #define UART_INTR_PARE 0x00000080 #define UART_INTR_TIMEOUT 0x00000100 #define UART_INTR_DMSI 0x00000200 +#define UART_INTR_TOVR 0x00001000 #define UART_SR_RACTIVE 0x00000400 #define UART_SR_TACTIVE 0x00000800 |