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| author | Luc Michel <luc.michel@amd.com> | 2025-07-16 11:53:43 +0200 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <philmd@linaro.org> | 2025-07-29 13:56:39 +0200 |
| commit | 2bfcd27e00a49da2efa5d703121b94cd9cd4948b (patch) | |
| tree | a67e9a49a3364bcea764ae56b1af2a7e9bfc1989 | |
| parent | b496a392fec656d8e7af81c496efa3d45fd59023 (diff) | |
| download | qemu-2bfcd27e00a49da2efa5d703121b94cd9cd4948b.zip qemu-2bfcd27e00a49da2efa5d703121b94cd9cd4948b.tar.gz qemu-2bfcd27e00a49da2efa5d703121b94cd9cd4948b.tar.bz2 | |
hw/net/cadence_gem: fix register mask initialization
The gem_init_register_masks function was called at init time but it
relies on the num-priority-queues property. Call it at realize time
instead.
Cc: qemu-stable@nongnu.org
Fixes: 4c70e32f05f ("net: cadence_gem: Define access permission for interrupt registers")
Signed-off-by: Luc Michel <luc.michel@amd.com>
Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
Reviewed-by: Sai Pavan Boddu <sai.pavan.boddu@amd.com>
Message-ID: <20250716095432.81923-2-luc.michel@amd.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
| -rw-r--r-- | hw/net/cadence_gem.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index 50025d5..4444666 100644 --- a/hw/net/cadence_gem.c +++ b/hw/net/cadence_gem.c @@ -1756,6 +1756,7 @@ static void gem_realize(DeviceState *dev, Error **errp) sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]); } + gem_init_register_masks(s); qemu_macaddr_default_if_unset(&s->conf.macaddr); s->nic = qemu_new_nic(&net_gem_info, &s->conf, @@ -1776,7 +1777,6 @@ static void gem_init(Object *obj) DB_PRINT("\n"); - gem_init_register_masks(s); memory_region_init_io(&s->iomem, OBJECT(s), &gem_ops, s, "enet", sizeof(s->regs)); |