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author | Aurelien Jarno <aurelien@aurel32.net> | 2012-10-09 21:53:21 +0200 |
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committer | Aurelien Jarno <aurelien@aurel32.net> | 2012-10-31 22:20:49 +0100 |
commit | 286d52ebfc0d0d53c2a878e454292fea14bad41b (patch) | |
tree | 3d9d22ff1768c50c468f3c9e40523159a9cd7ac2 | |
parent | bc3e45e13a93b883f0369acb2e19c0cec8705a7a (diff) | |
download | qemu-286d52ebfc0d0d53c2a878e454292fea14bad41b.zip qemu-286d52ebfc0d0d53c2a878e454292fea14bad41b.tar.gz qemu-286d52ebfc0d0d53c2a878e454292fea14bad41b.tar.bz2 |
target-mips: don't flush extra TLB on permissions upgrade
If the guest uses a TLBWI instruction for upgrading permissions, we
don't need to flush the extra TLBs. This improve boot time performance
by about 10%.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
-rw-r--r-- | target-mips/op_helper.c | 28 |
1 files changed, 23 insertions, 5 deletions
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c index cdd6880..f45d494 100644 --- a/target-mips/op_helper.c +++ b/target-mips/op_helper.c @@ -1819,14 +1819,32 @@ static void r4k_fill_tlb(CPUMIPSState *env, int idx) void r4k_helper_tlbwi(CPUMIPSState *env) { + r4k_tlb_t *tlb; int idx; + target_ulong VPN; + uint8_t ASID; + bool G, V0, D0, V1, D1; idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb; - - /* Discard cached TLB entries. We could avoid doing this if the - tlbwi is just upgrading access permissions on the current entry; - that might be a further win. */ - r4k_mips_tlb_flush_extra (env, env->tlb->nb_tlb); + tlb = &env->tlb->mmu.r4k.tlb[idx]; + VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1); +#if defined(TARGET_MIPS64) + VPN &= env->SEGMask; +#endif + ASID = env->CP0_EntryHi & 0xff; + G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1; + V0 = (env->CP0_EntryLo0 & 2) != 0; + D0 = (env->CP0_EntryLo0 & 4) != 0; + V1 = (env->CP0_EntryLo1 & 2) != 0; + D1 = (env->CP0_EntryLo1 & 4) != 0; + + /* Discard cached TLB entries, unless tlbwi is just upgrading access + permissions on the current entry. */ + if (tlb->VPN != VPN || tlb->ASID != ASID || tlb->G != G || + (tlb->V0 && !V0) || (tlb->D0 && !D0) || + (tlb->V1 && !V1) || (tlb->D1 && !D1)) { + r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb); + } r4k_invalidate_tlb(env, idx, 0); r4k_fill_tlb(env, idx); |