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author | Taylor Simpson <tsimpson@quicinc.com> | 2023-04-27 15:59:59 -0700 |
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committer | Taylor Simpson <tsimpson@quicinc.com> | 2023-05-18 12:40:52 -0700 |
commit | 25e1d87d1041a27c1f34480b53059faeb6600fef (patch) | |
tree | 576b6915c7e2745fabc87ca670c53b42fa6fab5b | |
parent | d24f0b2b89d0f4f595a1b62c00c4c951d1d5fce9 (diff) | |
download | qemu-25e1d87d1041a27c1f34480b53059faeb6600fef.zip qemu-25e1d87d1041a27c1f34480b53059faeb6600fef.tar.gz qemu-25e1d87d1041a27c1f34480b53059faeb6600fef.tar.bz2 |
Hexagon (target/hexagon) Clean up pred_written usage
Only endloop instructions will conditionally write to a predicate.
When there is an endloop instruction, we preload the values into
new_pred_value.
The only place pred_written is needed is when HEX_DEBUG is on.
We remove the last use of check_for_attrib. However, new uses will be
introduced later in this series, so we mark it with G_GNUC_UNUSED.
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230427230012.3800327-9-tsimpson@quicinc.com>
-rw-r--r-- | target/hexagon/genptr.c | 16 | ||||
-rw-r--r-- | target/hexagon/translate.c | 53 |
2 files changed, 23 insertions, 46 deletions
diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c index dac62b9..9bbaca6 100644 --- a/target/hexagon/genptr.c +++ b/target/hexagon/genptr.c @@ -137,7 +137,9 @@ void gen_log_pred_write(DisasContext *ctx, int pnum, TCGv val) tcg_gen_and_tl(hex_new_pred_value[pnum], hex_new_pred_value[pnum], base_val); } - tcg_gen_ori_tl(hex_pred_written, hex_pred_written, 1 << pnum); + if (HEX_DEBUG) { + tcg_gen_ori_tl(hex_pred_written, hex_pred_written, 1 << pnum); + } set_bit(pnum, ctx->pregs_written); } @@ -826,15 +828,13 @@ static void gen_endloop0(DisasContext *ctx) /* * if (lpcfg == 1) { - * hex_new_pred_value[3] = 0xff; - * hex_pred_written |= 1 << 3; + * p3 = 0xff; * } */ TCGLabel *label1 = gen_new_label(); tcg_gen_brcondi_tl(TCG_COND_NE, lpcfg, 1, label1); { - tcg_gen_movi_tl(hex_new_pred_value[3], 0xff); - tcg_gen_ori_tl(hex_pred_written, hex_pred_written, 1 << 3); + gen_log_pred_write(ctx, 3, tcg_constant_tl(0xff)); } gen_set_label(label1); @@ -903,14 +903,12 @@ static void gen_endloop01(DisasContext *ctx) /* * if (lpcfg == 1) { - * hex_new_pred_value[3] = 0xff; - * hex_pred_written |= 1 << 3; + * p3 = 0xff; * } */ tcg_gen_brcondi_tl(TCG_COND_NE, lpcfg, 1, label1); { - tcg_gen_movi_tl(hex_new_pred_value[3], 0xff); - tcg_gen_ori_tl(hex_pred_written, hex_pred_written, 1 << 3); + gen_log_pred_write(ctx, 3, tcg_constant_tl(0xff)); } gen_set_label(label1); diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index 01f448a..0b021b3 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -239,7 +239,7 @@ static int read_packet_words(CPUHexagonState *env, DisasContext *ctx, return nwords; } -static bool check_for_attrib(Packet *pkt, int attrib) +static G_GNUC_UNUSED bool check_for_attrib(Packet *pkt, int attrib) { for (int i = 0; i < pkt->num_insns; i++) { if (GET_ATTRIB(pkt->insn[i].opcode, attrib)) { @@ -262,11 +262,6 @@ static bool need_slot_cancelled(Packet *pkt) return false; } -static bool need_pred_written(Packet *pkt) -{ - return check_for_attrib(pkt, A_WRITES_PRED_REG); -} - static bool need_next_PC(DisasContext *ctx) { Packet *pkt = ctx->pkt; @@ -414,7 +409,7 @@ static void gen_start_packet(DisasContext *ctx) tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], next_PC); } } - if (need_pred_written(pkt)) { + if (HEX_DEBUG) { tcg_gen_movi_tl(hex_pred_written, 0); } @@ -428,6 +423,17 @@ static void gen_start_packet(DisasContext *ctx) } } + /* + * Preload the predicated pred registers into hex_new_pred_value[pred_num] + * Only endloop instructions conditionally write to pred registers + */ + if (pkt->pkt_has_endloop) { + for (int i = 0; i < ctx->preg_log_idx; i++) { + int pred_num = ctx->preg_log[i]; + tcg_gen_mov_tl(hex_new_pred_value[pred_num], hex_pred[pred_num]); + } + } + /* Preload the predicated HVX registers into future_VRegs and tmp_VRegs */ if (!bitmap_empty(ctx->predicated_future_vregs, NUM_VREGS)) { int i = find_first_bit(ctx->predicated_future_vregs, NUM_VREGS); @@ -535,41 +541,14 @@ static void gen_reg_writes(DisasContext *ctx) static void gen_pred_writes(DisasContext *ctx) { - int i; - /* Early exit if the log is empty */ if (!ctx->preg_log_idx) { return; } - /* - * Only endloop instructions will conditionally - * write a predicate. If there are no endloop - * instructions, we can use the non-conditional - * write of the predicates. - */ - if (ctx->pkt->pkt_has_endloop) { - TCGv zero = tcg_constant_tl(0); - TCGv pred_written = tcg_temp_new(); - for (i = 0; i < ctx->preg_log_idx; i++) { - int pred_num = ctx->preg_log[i]; - - tcg_gen_andi_tl(pred_written, hex_pred_written, 1 << pred_num); - tcg_gen_movcond_tl(TCG_COND_NE, hex_pred[pred_num], - pred_written, zero, - hex_new_pred_value[pred_num], - hex_pred[pred_num]); - } - } else { - for (i = 0; i < ctx->preg_log_idx; i++) { - int pred_num = ctx->preg_log[i]; - tcg_gen_mov_tl(hex_pred[pred_num], hex_new_pred_value[pred_num]); - if (HEX_DEBUG) { - /* Do this so HELPER(debug_commit_end) will know */ - tcg_gen_ori_tl(hex_pred_written, hex_pred_written, - 1 << pred_num); - } - } + for (int i = 0; i < ctx->preg_log_idx; i++) { + int pred_num = ctx->preg_log[i]; + tcg_gen_mov_tl(hex_pred[pred_num], hex_new_pred_value[pred_num]); } } |