diff options
author | Rob Bradford <rbradford@rivosinc.com> | 2023-10-31 15:37:15 +0000 |
---|---|---|
committer | Alistair Francis <alistair.francis@wdc.com> | 2023-11-07 11:06:02 +1000 |
commit | 2571a6427c4ded57e44d4c6cf92376d869a75a5c (patch) | |
tree | bcec662289cc1659737cd0bb5204a65ee89373d9 | |
parent | 7c1bb1d8d412f03ec7d6042971892bd0dff222b7 (diff) | |
download | qemu-2571a6427c4ded57e44d4c6cf92376d869a75a5c.zip qemu-2571a6427c4ded57e44d4c6cf92376d869a75a5c.tar.gz qemu-2571a6427c4ded57e44d4c6cf92376d869a75a5c.tar.bz2 |
target/riscv: Use existing PMU counter mask in FDT generation
During the FDT generation use the existing mask containing the enabled
counters rather then generating a new one. Using the existing mask will
support the use of discontinuous counters.
Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Message-ID: <20231031154000.18134-4-rbradford@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
-rw-r--r-- | hw/riscv/virt.c | 2 | ||||
-rw-r--r-- | target/riscv/pmu.c | 6 | ||||
-rw-r--r-- | target/riscv/pmu.h | 2 |
3 files changed, 3 insertions, 7 deletions
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 1732c42..c7fc97e 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -722,7 +722,7 @@ static void create_fdt_pmu(RISCVVirtState *s) pmu_name = g_strdup_printf("/pmu"); qemu_fdt_add_subnode(ms->fdt, pmu_name); qemu_fdt_setprop_string(ms->fdt, pmu_name, "compatible", "riscv,pmu"); - riscv_pmu_generate_fdt_node(ms->fdt, hart.cfg.pmu_num, pmu_name); + riscv_pmu_generate_fdt_node(ms->fdt, hart.pmu_avail_ctrs, pmu_name); g_free(pmu_name); } diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c index 13801cc..7ddf497 100644 --- a/target/riscv/pmu.c +++ b/target/riscv/pmu.c @@ -34,13 +34,9 @@ * to provide the correct value as well. Heterogeneous PMU per hart is not * supported yet. Thus, number of counters are same across all harts. */ -void riscv_pmu_generate_fdt_node(void *fdt, int num_ctrs, char *pmu_name) +void riscv_pmu_generate_fdt_node(void *fdt, uint32_t cmask, char *pmu_name) { uint32_t fdt_event_ctr_map[15] = {}; - uint32_t cmask; - - /* All the programmable counters can map to any event */ - cmask = MAKE_32BIT_MASK(3, num_ctrs); /* * The event encoding is specified in the SBI specification diff --git a/target/riscv/pmu.h b/target/riscv/pmu.h index 88e0713..505fc85 100644 --- a/target/riscv/pmu.h +++ b/target/riscv/pmu.h @@ -28,6 +28,6 @@ void riscv_pmu_init(RISCVCPU *cpu, Error **errp); int riscv_pmu_update_event_map(CPURISCVState *env, uint64_t value, uint32_t ctr_idx); int riscv_pmu_incr_ctr(RISCVCPU *cpu, enum riscv_pmu_event_idx event_idx); -void riscv_pmu_generate_fdt_node(void *fdt, int num_counters, char *pmu_name); +void riscv_pmu_generate_fdt_node(void *fdt, uint32_t cmask, char *pmu_name); int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t value, uint32_t ctr_idx); |