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| author | Richard Henderson <richard.henderson@linaro.org> | 2022-12-07 17:50:15 +0000 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2023-01-06 23:07:04 +0000 |
| commit | 238da1c942037412033a08288f73bc9815bb8c2c (patch) | |
| tree | d0db1bea27a5f028cf7ce5b918c2553afa7ff1ff | |
| parent | e62d5752f5e7fdddb6b309230589281d9fa4d609 (diff) | |
| download | qemu-238da1c942037412033a08288f73bc9815bb8c2c.zip qemu-238da1c942037412033a08288f73bc9815bb8c2c.tar.gz qemu-238da1c942037412033a08288f73bc9815bb8c2c.tar.bz2 | |
tcg/s390x: Remove DISTINCT_OPERANDS facility check
The distinct-operands facility is bundled into facility 45,
along with load-on-condition. We are checking this at startup.
Remove the a0 == a1 checks for 64-bit sub, and, or, xor, as there
is no space savings for avoiding the distinct-operands insn.
Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| -rw-r--r-- | tcg/s390x/tcg-target.c.inc | 16 | ||||
| -rw-r--r-- | tcg/s390x/tcg-target.h | 1 |
2 files changed, 2 insertions, 15 deletions
diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index dd58f0c..e4403ff 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -2218,8 +2218,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, if (const_args[2]) { a2 = -a2; goto do_addi_64; - } else if (a0 == a1) { - tcg_out_insn(s, RRE, SGR, a0, a2); } else { tcg_out_insn(s, RRF, SGRK, a0, a1, a2); } @@ -2230,8 +2228,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, if (const_args[2]) { tcg_out_mov(s, TCG_TYPE_I64, a0, a1); tgen_andi(s, TCG_TYPE_I64, args[0], args[2]); - } else if (a0 == a1) { - tcg_out_insn(s, RRE, NGR, args[0], args[2]); } else { tcg_out_insn(s, RRF, NGRK, a0, a1, a2); } @@ -2241,8 +2237,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, if (const_args[2]) { tcg_out_mov(s, TCG_TYPE_I64, a0, a1); tgen_ori(s, TCG_TYPE_I64, a0, a2); - } else if (a0 == a1) { - tcg_out_insn(s, RRE, OGR, a0, a2); } else { tcg_out_insn(s, RRF, OGRK, a0, a1, a2); } @@ -2252,8 +2246,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, if (const_args[2]) { tcg_out_mov(s, TCG_TYPE_I64, a0, a1); tgen_xori(s, TCG_TYPE_I64, a0, a2); - } else if (a0 == a1) { - tcg_out_insn(s, RRE, XGR, a0, a2); } else { tcg_out_insn(s, RRF, XGRK, a0, a1, a2); } @@ -2926,9 +2918,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_or_i64: case INDEX_op_xor_i32: case INDEX_op_xor_i64: - return (HAVE_FACILITY(DISTINCT_OPS) - ? C_O1_I2(r, r, ri) - : C_O1_I2(r, 0, ri)); + return C_O1_I2(r, r, ri); case INDEX_op_mul_i32: return C_O1_I2(r, 0, ri); @@ -2938,9 +2928,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_shl_i32: case INDEX_op_shr_i32: case INDEX_op_sar_i32: - return (HAVE_FACILITY(DISTINCT_OPS) - ? C_O1_I2(r, r, ri) - : C_O1_I2(r, 0, ri)); + return C_O1_I2(r, r, ri); case INDEX_op_brcond_i32: case INDEX_op_brcond_i64: diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h index fc9ae82..db10a39 100644 --- a/tcg/s390x/tcg-target.h +++ b/tcg/s390x/tcg-target.h @@ -62,7 +62,6 @@ typedef enum TCGReg { /* Facilities that are checked at runtime. */ -#define FACILITY_DISTINCT_OPS 45 #define FACILITY_LOAD_ON_COND2 53 #define FACILITY_VECTOR 129 #define FACILITY_VECTOR_ENH1 135 |