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| author | Rob Bradford <rbradford@rivosinc.com> | 2024-01-11 16:16:43 +0000 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2024-02-09 10:39:16 +1000 |
| commit | 2317ba9fa7f39402fec17847afe11b99e361d9a0 (patch) | |
| tree | 31dda0230fdcf91ad714d75bde33bae96caab5c1 | |
| parent | 878502e5fe58b7061a631275c1db9fa4f1442479 (diff) | |
| download | qemu-2317ba9fa7f39402fec17847afe11b99e361d9a0.zip qemu-2317ba9fa7f39402fec17847afe11b99e361d9a0.tar.gz qemu-2317ba9fa7f39402fec17847afe11b99e361d9a0.tar.bz2 | |
target/riscv: Add infrastructure for 'B' MISA extension
Add the infrastructure for the 'B' extension which is the union of the
Zba, Zbb and Zbs instructions.
Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240111161644.33630-2-rbradford@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| -rw-r--r-- | target/riscv/cpu.c | 5 | ||||
| -rw-r--r-- | target/riscv/cpu.h | 1 | ||||
| -rw-r--r-- | target/riscv/tcg/tcg-cpu.c | 1 |
3 files changed, 5 insertions, 2 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index be21fa0..8a2fd7d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -38,9 +38,9 @@ #include "tcg/tcg.h" /* RISC-V CPU definitions */ -static const char riscv_single_letter_exts[] = "IEMAFDQCPVH"; +static const char riscv_single_letter_exts[] = "IEMAFDQCBPVH"; const uint32_t misa_bits[] = {RVI, RVE, RVM, RVA, RVF, RVD, RVV, - RVC, RVS, RVU, RVH, RVJ, RVG, 0}; + RVC, RVS, RVU, RVH, RVJ, RVG, RVB, 0}; /* * From vector_helper.c @@ -1304,6 +1304,7 @@ static const MISAExtInfo misa_ext_info_arr[] = { MISA_EXT_INFO(RVJ, "x-j", "Dynamic translated languages"), MISA_EXT_INFO(RVV, "v", "Vector operations"), MISA_EXT_INFO(RVG, "g", "General purpose (IMAFD_Zicsr_Zifencei)"), + MISA_EXT_INFO(RVB, "x-b", "Bit manipulation (Zba_Zbb_Zbs)") }; static int riscv_validate_misa_info_idx(uint32_t bit) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index f63ee9c..136fc1d 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -69,6 +69,7 @@ typedef struct CPUArchState CPURISCVState; #define RVH RV('H') #define RVJ RV('J') #define RVG RV('G') +#define RVB RV('B') extern const uint32_t misa_bits[]; const char *riscv_get_misa_ext_name(uint32_t bit); diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index b7da927..baecfa7 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -1056,6 +1056,7 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = { MISA_CFG(RVJ, false), MISA_CFG(RVV, false), MISA_CFG(RVG, false), + MISA_CFG(RVB, false), }; /* |