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| author | Philippe Mathieu-Daudé <philmd@linaro.org> | 2024-01-18 21:06:36 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2024-01-26 11:30:49 +0000 |
| commit | 22036ae5773ab46eeee412c0aa3ec2eb1e4008e7 (patch) | |
| tree | 9c0a6a1556b36e411592c82cec1b302d336fc4eb | |
| parent | 3e283646e7524e3f0346431c27d03aa53198c8ad (diff) | |
| download | qemu-22036ae5773ab46eeee412c0aa3ec2eb1e4008e7.zip qemu-22036ae5773ab46eeee412c0aa3ec2eb1e4008e7.tar.gz qemu-22036ae5773ab46eeee412c0aa3ec2eb1e4008e7.tar.bz2 | |
target/arm: Expose M-profile register bank index definitions
The ARMv7M QDev container accesses the QDev SysTickState
by its secure/non-secure bank index. In order to make
the "hw/intc/armv7m_nvic.h" header target-agnostic in
the next commit, first move the M-profile bank index
definitions to "target/arm/cpu-qom.h".
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240118200643.29037-16-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | target/arm/cpu-qom.h | 15 | ||||
| -rw-r--r-- | target/arm/cpu.h | 15 |
2 files changed, 15 insertions, 15 deletions
diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h index f795994..77bbc1f 100644 --- a/target/arm/cpu-qom.h +++ b/target/arm/cpu-qom.h @@ -36,4 +36,19 @@ DECLARE_CLASS_CHECKERS(AArch64CPUClass, AARCH64_CPU, #define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) +/* For M profile, some registers are banked secure vs non-secure; + * these are represented as a 2-element array where the first element + * is the non-secure copy and the second is the secure copy. + * When the CPU does not have implement the security extension then + * only the first element is used. + * This means that the copy for the current security state can be + * accessed via env->registerfield[env->v7m.secure] (whether the security + * extension is implemented or not). + */ +enum { + M_REG_NS = 0, + M_REG_S = 1, + M_REG_NUM_BANKS = 2, +}; + #endif diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 41659d0..d6a7948 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -73,21 +73,6 @@ #define ARMV7M_EXCP_PENDSV 14 #define ARMV7M_EXCP_SYSTICK 15 -/* For M profile, some registers are banked secure vs non-secure; - * these are represented as a 2-element array where the first element - * is the non-secure copy and the second is the secure copy. - * When the CPU does not have implement the security extension then - * only the first element is used. - * This means that the copy for the current security state can be - * accessed via env->registerfield[env->v7m.secure] (whether the security - * extension is implemented or not). - */ -enum { - M_REG_NS = 0, - M_REG_S = 1, - M_REG_NUM_BANKS = 2, -}; - /* ARM-specific interrupt pending bits. */ #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 |