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| author | Zhao Liu <zhao1.liu@intel.com> | 2025-01-10 22:51:12 +0800 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2025-02-25 16:18:12 +0100 |
| commit | 2152b4bfcd91d7d8b99cd502ed049b0ab8e38649 (patch) | |
| tree | eb37492ffa72d024a08fce63ad40d0e6fd8873c9 | |
| parent | d556226d6965738e06a1d75faaf271b769bb5880 (diff) | |
| download | qemu-2152b4bfcd91d7d8b99cd502ed049b0ab8e38649.zip qemu-2152b4bfcd91d7d8b99cd502ed049b0ab8e38649.tar.gz qemu-2152b4bfcd91d7d8b99cd502ed049b0ab8e38649.tar.bz2 | |
i386/cpu: Support module level cache topology
Allow cache to be defined at the module level. This increases
flexibility for x86 users to customize their cache topology.
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Tested-by: Yongwei Ma <yongwei.ma@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Link: https://lore.kernel.org/r/20250110145115.1574345-3-zhao1.liu@intel.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| -rw-r--r-- | target/i386/cpu.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 72ab147..8799e22 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -247,6 +247,9 @@ static uint32_t max_thread_ids_for_cache(X86CPUTopoInfo *topo_info, case CPU_TOPOLOGY_LEVEL_CORE: num_ids = 1 << apicid_core_offset(topo_info); break; + case CPU_TOPOLOGY_LEVEL_MODULE: + num_ids = 1 << apicid_module_offset(topo_info); + break; case CPU_TOPOLOGY_LEVEL_DIE: num_ids = 1 << apicid_die_offset(topo_info); break; @@ -255,7 +258,7 @@ static uint32_t max_thread_ids_for_cache(X86CPUTopoInfo *topo_info, break; default: /* - * Currently there is no use case for THREAD and MODULE, so use + * Currently there is no use case for THREAD, so use * assert directly to facilitate debugging. */ g_assert_not_reached(); |