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| author | Richard Henderson <richard.henderson@linaro.org> | 2019-02-05 16:52:37 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2019-02-05 16:52:37 +0000 |
| commit | 1bafc2ba7e6bfe89fff3503fdac8db39c973de48 (patch) | |
| tree | 598335f5f41e58ee201e25ae684cc217d8ff45ec | |
| parent | d3765835ed02f91f0c6cbb452874209a6af4a730 (diff) | |
| download | qemu-1bafc2ba7e6bfe89fff3503fdac8db39c973de48.zip qemu-1bafc2ba7e6bfe89fff3503fdac8db39c973de48.tar.gz qemu-1bafc2ba7e6bfe89fff3503fdac8db39c973de48.tar.bz2 | |
target/arm: Cache the GP bit for a page in MemTxAttrs
Caching the bit means that we will not have to re-walk the
page tables to look up the bit during translation.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20190128223118.5255-6-richard.henderson@linaro.org
[PMM: no need to OR in guarded bit status]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | target/arm/helper.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/target/arm/helper.c b/target/arm/helper.c index 45ba678..be0ec7d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10577,6 +10577,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, bool ttbr1_valid; uint64_t descaddrmask; bool aarch64 = arm_el_is_aa64(env, el); + bool guarded = false; /* TODO: * This code does not handle the different format TCR for VTCR_EL2. @@ -10756,6 +10757,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, } /* Merge in attributes from table descriptors */ attrs |= nstable << 3; /* NS */ + guarded = extract64(descriptor, 50, 1); /* GP */ if (param.hpd) { /* HPD disables all the table attributes except NSTable. */ break; @@ -10801,6 +10803,10 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, */ txattrs->secure = false; } + /* When in aarch64 mode, and BTI is enabled, remember GP in the IOTLB. */ + if (aarch64 && guarded && cpu_isar_feature(aa64_bti, cpu)) { + txattrs->target_tlb_bit0 = true; + } if (cacheattrs != NULL) { if (mmu_idx == ARMMMUIdx_S2NS) { |