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| author | Aleksandar Markovic <amarkovic@wavecomp.com> | 2019-08-28 18:26:25 +0200 |
|---|---|---|
| committer | Aleksandar Markovic <amarkovic@wavecomp.com> | 2019-08-29 11:50:18 +0200 |
| commit | 1b142da5f82a8fcdc7783a418592de654d5c6052 (patch) | |
| tree | 80ee001b778551f2fc2812015fb91944f9f13f0d | |
| parent | 705be570941b38cd1cbebc68f7f671ce7532ecb0 (diff) | |
| download | qemu-1b142da5f82a8fcdc7783a418592de654d5c6052.zip qemu-1b142da5f82a8fcdc7783a418592de654d5c6052.tar.gz qemu-1b142da5f82a8fcdc7783a418592de654d5c6052.tar.bz2 | |
target/mips: Clean up handling of CP0 register 0
Clean up handling of CP0 register 0.
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1567009614-12438-2-git-send-email-aleksandar.markovic@rt-rk.com>
| -rw-r--r-- | target/mips/cpu.h | 3 | ||||
| -rw-r--r-- | target/mips/translate.c | 40 |
2 files changed, 23 insertions, 20 deletions
diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 1fd4a18..42d0e44 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -277,6 +277,9 @@ typedef struct mips_def_t mips_def_t; /* CP0 Register 00 */ #define CP0_REG00__INDEX 0 +#define CP0_REG00__MVPCONTROL 1 +#define CP0_REG00__MVPCONF0 2 +#define CP0_REG00__MVPCONF1 3 #define CP0_REG00__VPCONTROL 4 /* CP0 Register 01 */ /* CP0 Register 02 */ diff --git a/target/mips/translate.c b/target/mips/translate.c index 8ebde6f..c3fcfb4 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -6813,26 +6813,26 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) switch (reg) { case CP0_REGISTER_00: switch (sel) { - case 0: + case CP0_REG00__INDEX: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Index)); register_name = "Index"; break; - case 1: + case CP0_REG00__MVPCONTROL: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_mfc0_mvpcontrol(arg, cpu_env); register_name = "MVPControl"; break; - case 2: + case CP0_REG00__MVPCONF0: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_mfc0_mvpconf0(arg, cpu_env); register_name = "MVPConf0"; break; - case 3: + case CP0_REG00__MVPCONF1: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_mfc0_mvpconf1(arg, cpu_env); register_name = "MVPConf1"; break; - case 4: + case CP0_REG00__VPCONTROL: CP0_CHECK(ctx->vp); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPControl)); register_name = "VPControl"; @@ -7573,26 +7573,26 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) switch (reg) { case CP0_REGISTER_00: switch (sel) { - case 0: + case CP0_REG00__INDEX: gen_helper_mtc0_index(cpu_env, arg); register_name = "Index"; break; - case 1: + case CP0_REG00__MVPCONTROL: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_mtc0_mvpcontrol(cpu_env, arg); register_name = "MVPControl"; break; - case 2: + case CP0_REG00__MVPCONF0: CP0_CHECK(ctx->insn_flags & ASE_MT); /* ignored */ register_name = "MVPConf0"; break; - case 3: + case CP0_REG00__MVPCONF1: CP0_CHECK(ctx->insn_flags & ASE_MT); /* ignored */ register_name = "MVPConf1"; break; - case 4: + case CP0_REG00__VPCONTROL: CP0_CHECK(ctx->vp); /* ignored */ register_name = "VPControl"; @@ -8319,26 +8319,26 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel) switch (reg) { case CP0_REGISTER_00: switch (sel) { - case 0: + case CP0_REG00__INDEX: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Index)); register_name = "Index"; break; - case 1: + case CP0_REG00__MVPCONTROL: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_mfc0_mvpcontrol(arg, cpu_env); register_name = "MVPControl"; break; - case 2: + case CP0_REG00__MVPCONF0: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_mfc0_mvpconf0(arg, cpu_env); register_name = "MVPConf0"; break; - case 3: + case CP0_REG00__MVPCONF1: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_mfc0_mvpconf1(arg, cpu_env); register_name = "MVPConf1"; break; - case 4: + case CP0_REG00__VPCONTROL: CP0_CHECK(ctx->vp); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPControl)); register_name = "VPControl"; @@ -9033,26 +9033,26 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) switch (reg) { case CP0_REGISTER_00: switch (sel) { - case 0: + case CP0_REG00__INDEX: gen_helper_mtc0_index(cpu_env, arg); register_name = "Index"; break; - case 1: + case CP0_REG00__MVPCONTROL: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_mtc0_mvpcontrol(cpu_env, arg); register_name = "MVPControl"; break; - case 2: + case CP0_REG00__MVPCONF0: CP0_CHECK(ctx->insn_flags & ASE_MT); /* ignored */ register_name = "MVPConf0"; break; - case 3: + case CP0_REG00__MVPCONF1: CP0_CHECK(ctx->insn_flags & ASE_MT); /* ignored */ register_name = "MVPConf1"; break; - case 4: + case CP0_REG00__VPCONTROL: CP0_CHECK(ctx->vp); /* ignored */ register_name = "VPControl"; |