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| author | Yongbok Kim <yongbok.kim@mips.com> | 2019-01-03 14:12:48 +0100 |
|---|---|---|
| committer | Aleksandar Markovic <amarkovic@wavecomp.com> | 2019-01-18 16:53:28 +0100 |
| commit | 167db30e981cd72bef15182178037e51afc8e40d (patch) | |
| tree | e96593cc3bd2de7a49ab5dba52cbd9e057aa3fd5 | |
| parent | 46d7642fcc97ac108c8080fbe41bc5d00bb537f2 (diff) | |
| download | qemu-167db30e981cd72bef15182178037e51afc8e40d.zip qemu-167db30e981cd72bef15182178037e51afc8e40d.tar.gz qemu-167db30e981cd72bef15182178037e51afc8e40d.tar.bz2 | |
target/mips: Add fields for SAARI and SAAR CP0 registers
Add fields for SAARI and SAAR CP0 registers.
Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
| -rw-r--r-- | target/mips/cpu.h | 10 | ||||
| -rw-r--r-- | target/mips/machine.c | 6 |
2 files changed, 12 insertions, 4 deletions
diff --git a/target/mips/cpu.h b/target/mips/cpu.h index b095422..1c2c682 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -164,8 +164,8 @@ typedef struct mips_def_t mips_def_t; * 3 BadInstrX * 4 GuestCtl1 GuestCtl0Ext * 5 GuestCtl2 - * 6 GuestCtl3 - * 7 + * 6 SAARI GuestCtl3 + * 7 SAAR * * * Register 12 Register 13 Register 14 Register 15 @@ -546,6 +546,12 @@ struct CPUMIPSState { * CP0 Register 9 */ int32_t CP0_Count; + uint32_t CP0_SAARI; +#define CP0SAARI_TARGET 0 /* 5..0 */ + uint64_t CP0_SAAR[2]; +#define CP0SAAR_BASE 12 /* 43..12 */ +#define CP0SAAR_SIZE 1 /* 5..1 */ +#define CP0SAAR_EN 0 /* * CP0 Register 10 */ diff --git a/target/mips/machine.c b/target/mips/machine.c index 704e9c0..111d7c3 100644 --- a/target/mips/machine.c +++ b/target/mips/machine.c @@ -214,8 +214,8 @@ const VMStateDescription vmstate_tlb = { const VMStateDescription vmstate_mips_cpu = { .name = "cpu", - .version_id = 15, - .minimum_version_id = 15, + .version_id = 16, + .minimum_version_id = 16, .post_load = cpu_post_load, .fields = (VMStateField[]) { /* Active TC */ @@ -274,6 +274,8 @@ const VMStateDescription vmstate_mips_cpu = { VMSTATE_UINT32(env.CP0_BadInstrP, MIPSCPU), VMSTATE_UINT32(env.CP0_BadInstrX, MIPSCPU), VMSTATE_INT32(env.CP0_Count, MIPSCPU), + VMSTATE_UINT32(env.CP0_SAARI, MIPSCPU), + VMSTATE_UINT64_ARRAY(env.CP0_SAAR, MIPSCPU, 2), VMSTATE_UINTTL(env.CP0_EntryHi, MIPSCPU), VMSTATE_INT32(env.CP0_Compare, MIPSCPU), VMSTATE_INT32(env.CP0_Status, MIPSCPU), |