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| author | Jerry Zhang Jian <jerry.zhangjian@sifive.com> | 2024-05-28 21:03:49 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2024-06-26 22:30:52 +1000 |
| commit | 15b8ddb18ae0be3f3921cab7169fa562b77227e0 (patch) | |
| tree | 60d78e46a354770156f6e65fb591ac929d743fa5 | |
| parent | 92c82a126e633c51ac01b6fc158123aca96dddf6 (diff) | |
| download | qemu-15b8ddb18ae0be3f3921cab7169fa562b77227e0.zip qemu-15b8ddb18ae0be3f3921cab7169fa562b77227e0.tar.gz qemu-15b8ddb18ae0be3f3921cab7169fa562b77227e0.tar.bz2 | |
target/riscv: zvbb implies zvkb
According to RISC-V crypto spec, Zvkb extension is a
subset of the Zvbb extension [1].
1: https://github.com/riscv/riscv-crypto/blob/1769c2609bf4535632e0c0fd715778f212bb272e/doc/vector/riscv-crypto-vector-zvkb.adoc?plain=1#L10
Signed-off-by: Jerry Zhang Jian <jerry.zhangjian@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240528130349.20193-1-jerry.zhangjian@sifive.com>
[ Changes by AF:
- Tidy up commit message
- Rebase
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| -rw-r--r-- | target/riscv/tcg/tcg-cpu.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 683f604..fa8a17c 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -667,6 +667,10 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true); } + if (cpu->cfg.ext_zvbb) { + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkb), true); + } + if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkb || cpu->cfg.ext_zvkg || cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed || cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32x) { |