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| author | Aleksandar Markovic <amarkovic@wavecomp.com> | 2019-08-28 18:26:45 +0200 |
|---|---|---|
| committer | Aleksandar Markovic <amarkovic@wavecomp.com> | 2019-08-29 12:05:51 +0200 |
| commit | 14f92b0b9ca0abe48f9a23a73e8dc413d919eab9 (patch) | |
| tree | cb1c3bb64089473c5788ff2f497862ec41898ec5 | |
| parent | be274dc18ee3682bb3a2ba7e5ccd3061b103cbec (diff) | |
| download | qemu-14f92b0b9ca0abe48f9a23a73e8dc413d919eab9.zip qemu-14f92b0b9ca0abe48f9a23a73e8dc413d919eab9.tar.gz qemu-14f92b0b9ca0abe48f9a23a73e8dc413d919eab9.tar.bz2 | |
target/mips: Clean up handling of CP0 register 20
Clean up handling of CP0 register 20.
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1567009614-12438-22-git-send-email-aleksandar.markovic@rt-rk.com>
| -rw-r--r-- | target/mips/translate.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/target/mips/translate.c b/target/mips/translate.c index 6d617f4..55b0005 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -7341,7 +7341,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) break; case CP0_REGISTER_20: switch (sel) { - case 0: + case CP0_REG20__XCONTEXT: #if defined(TARGET_MIPS64) check_insn(ctx, ISA_MIPS3); tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_XContext)); @@ -8076,7 +8076,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) break; case CP0_REGISTER_20: switch (sel) { - case 0: + case CP0_REG20__XCONTEXT: #if defined(TARGET_MIPS64) check_insn(ctx, ISA_MIPS3); gen_helper_mtc0_xcontext(cpu_env, arg); @@ -8813,7 +8813,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel) break; case CP0_REGISTER_20: switch (sel) { - case 0: + case CP0_REG20__XCONTEXT: check_insn(ctx, ISA_MIPS3); tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_XContext)); register_name = "XContext"; @@ -9530,7 +9530,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) break; case CP0_REGISTER_20: switch (sel) { - case 0: + case CP0_REG20__XCONTEXT: check_insn(ctx, ISA_MIPS3); gen_helper_mtc0_xcontext(cpu_env, arg); register_name = "XContext"; |