diff options
| author | Andrew Jones <ajones@ventanamicro.com> | 2024-02-15 19:39:53 -0300 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2024-03-08 16:32:44 +1000 |
| commit | 148189ff1313e995a0a84957c496ff92965151a2 (patch) | |
| tree | 7ce06b7b152f547420897f625d3da4822e6da7b4 | |
| parent | a0952c15556d740a8dae88c7038ad5efe68745bc (diff) | |
| download | qemu-148189ff1313e995a0a84957c496ff92965151a2.zip qemu-148189ff1313e995a0a84957c496ff92965151a2.tar.gz qemu-148189ff1313e995a0a84957c496ff92965151a2.tar.bz2 | |
target/riscv: Reset henvcfg to zero
The hypervisor should decide what it wants to enable. Zero all
configuration enable bits on reset.
Also, commit ed67d63798f2 ("target/riscv: Update CSR bits name for
svadu extension") missed one reference to 'hade'. Change it now.
Fixes: 0af3f115e68e ("target/riscv: Add *envcfg.HADE related check in address translation")
Fixes: ed67d63798f2 ("target/riscv: Update CSR bits name for svadu extension")
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240215223955.969568-5-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| -rw-r--r-- | target/riscv/cpu.c | 3 | ||||
| -rw-r--r-- | target/riscv/csr.c | 2 |
2 files changed, 2 insertions, 3 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 4c4fa79..5507c11 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -961,8 +961,7 @@ static void riscv_cpu_reset_hold(Object *obj) env->menvcfg = (cpu->cfg.ext_svpbmt ? MENVCFG_PBMTE : 0) | (cpu->cfg.ext_svadu ? MENVCFG_ADUE : 0); - env->henvcfg = (cpu->cfg.ext_svpbmt ? HENVCFG_PBMTE : 0) | - (cpu->cfg.ext_svadu ? HENVCFG_ADUE : 0); + env->henvcfg = 0; /* Initialized default priorities of local interrupts. */ for (i = 0; i < ARRAY_SIZE(env->miprio); i++) { diff --git a/target/riscv/csr.c b/target/riscv/csr.c index d4e8ac1..cc9cef3 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -2133,7 +2133,7 @@ static RISCVException read_henvcfg(CPURISCVState *env, int csrno, /* * henvcfg.pbmte is read_only 0 when menvcfg.pbmte = 0 * henvcfg.stce is read_only 0 when menvcfg.stce = 0 - * henvcfg.hade is read_only 0 when menvcfg.hade = 0 + * henvcfg.adue is read_only 0 when menvcfg.adue = 0 */ *val = env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE) | env->menvcfg); |