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| author | Philippe Mathieu-Daudé <philmd@linaro.org> | 2023-06-26 22:36:10 +0200 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <philmd@linaro.org> | 2024-06-04 10:02:39 +0200 |
| commit | 14482b1360c34e1ccd3b9a6135aeff17ee3c8ee1 (patch) | |
| tree | 59742acf2c57ad9bfa79d42a17f2aa1afb5f347f | |
| parent | 7106121d26229f36ac0fb33e35bcb50513447582 (diff) | |
| download | qemu-14482b1360c34e1ccd3b9a6135aeff17ee3c8ee1.zip qemu-14482b1360c34e1ccd3b9a6135aeff17ee3c8ee1.tar.gz qemu-14482b1360c34e1ccd3b9a6135aeff17ee3c8ee1.tar.bz2 | |
target/riscv: Restrict 'rv128' machine to TCG accelerator
We only build for 32/64-bit hosts, so TCG is required for
128-bit targets.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230626232007.8933-5-philmd@linaro.org>
| -rw-r--r-- | target/riscv/cpu.c | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index eb1a2e7..0dad66e 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -591,6 +591,7 @@ static void rv64_veyron_v1_cpu_init(Object *obj) #endif } +#ifdef CONFIG_TCG static void rv128_base_cpu_init(Object *obj) { RISCVCPU *cpu = RISCV_CPU(obj); @@ -612,6 +613,7 @@ static void rv128_base_cpu_init(Object *obj) set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57); #endif } +#endif /* CONFIG_TCG */ static void rv64i_bare_cpu_init(Object *obj) { @@ -624,7 +626,9 @@ static void rv64e_bare_cpu_init(Object *obj) CPURISCVState *env = &RISCV_CPU(obj)->env; riscv_cpu_set_misa_ext(env, RVE); } -#else + +#else /* !TARGET_RISCV64 */ + static void rv32_base_cpu_init(Object *obj) { RISCVCPU *cpu = RISCV_CPU(obj); @@ -2550,12 +2554,14 @@ static const TypeInfo riscv_cpu_type_infos[] = { DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SHAKTI_C, MXL_RV64, rv64_sifive_u_cpu_init), DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_THEAD_C906, MXL_RV64, rv64_thead_c906_cpu_init), DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_VEYRON_V1, MXL_RV64, rv64_veyron_v1_cpu_init), +#ifdef CONFIG_TCG DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, MXL_RV128, rv128_base_cpu_init), +#endif /* CONFIG_TCG */ DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV64I, MXL_RV64, rv64i_bare_cpu_init), DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV64E, MXL_RV64, rv64e_bare_cpu_init), DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22U64, MXL_RV64, rva22u64_profile_cpu_init), DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22S64, MXL_RV64, rva22s64_profile_cpu_init), -#endif +#endif /* TARGET_RISCV64 */ }; DEFINE_TYPES(riscv_cpu_type_infos) |