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| author | Peter Maydell <peter.maydell@linaro.org> | 2024-12-11 15:30:57 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2024-12-11 15:30:57 +0000 |
| commit | 10519d3b1aeb24d8173631d4fe0ecb91f2732e19 (patch) | |
| tree | 18a39c3957123c2366dbea95b37f38df46597eb2 | |
| parent | 43e51128083185ec5deb2cbe322fb851f7e2d2ae (diff) | |
| download | qemu-10519d3b1aeb24d8173631d4fe0ecb91f2732e19.zip qemu-10519d3b1aeb24d8173631d4fe0ecb91f2732e19.tar.gz qemu-10519d3b1aeb24d8173631d4fe0ecb91f2732e19.tar.bz2 | |
target/arm: Set Float3NaNPropRule explicitly
Set the Float3NaNPropRule explicitly for Arm, and remove the
ifdef from pickNaNMulAdd().
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241202131347.498124-18-peter.maydell@linaro.org
| -rw-r--r-- | fpu/softfloat-specialize.c.inc | 8 | ||||
| -rw-r--r-- | target/arm/cpu.c | 5 |
2 files changed, 6 insertions, 7 deletions
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index b4f3f0e..3a2d044 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -505,13 +505,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, } if (rule == float_3nan_prop_none) { -#if defined(TARGET_ARM) - /* - * This looks different from the ARM ARM pseudocode, because the ARM ARM - * puts the operands to a fused mac operation (a*b)+c in the order c,a,b - */ - rule = float_3nan_prop_s_cab; -#elif defined(TARGET_MIPS) +#if defined(TARGET_MIPS) if (snan_bit_is_one(status)) { rule = float_3nan_prop_s_abc; } else { diff --git a/target/arm/cpu.c b/target/arm/cpu.c index ead3979..c81f6df 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -173,6 +173,10 @@ void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, * * tininess-before-rounding * * 2-input NaN propagation prefers SNaN over QNaN, and then * operand A over operand B (see FPProcessNaNs() pseudocode) + * * 3-input NaN propagation prefers SNaN over QNaN, and then + * operand C over A over B (see FPProcessNaNs3() pseudocode, + * but note that for QEMU muladd is a * b + c, whereas for + * the pseudocode function the arguments are in the order c, a, b. * * 0 * Inf + NaN returns the default NaN if the input NaN is quiet, * and the input NaN if it is signalling */ @@ -180,6 +184,7 @@ static void arm_set_default_fp_behaviours(float_status *s) { set_float_detect_tininess(float_tininess_before_rounding, s); set_float_2nan_prop_rule(float_2nan_prop_s_ab, s); + set_float_3nan_prop_rule(float_3nan_prop_s_cab, s); set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, s); } |