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| author | Philippe Mathieu-Daudé <philmd@linaro.org> | 2025-01-21 12:11:55 +0100 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <philmd@linaro.org> | 2025-03-09 17:00:47 +0100 |
| commit | 0ebdf989c32031019aa0974dbb6b840fca52991e (patch) | |
| tree | 9880ca827c97e431f0705d2fd1735e29e192b4b8 | |
| parent | bd7d74283464491b461bb1136e69963962fd05aa (diff) | |
| download | qemu-0ebdf989c32031019aa0974dbb6b840fca52991e.zip qemu-0ebdf989c32031019aa0974dbb6b840fca52991e.tar.gz qemu-0ebdf989c32031019aa0974dbb6b840fca52991e.tar.bz2 | |
target/arm: Prefer cached CpuClass over CPU_GET_CLASS() macro
CpuState caches its CPUClass since commit 6fbdff87062
("cpu: cache CPUClass in CPUState for hot code paths"),
use it.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20250122093028.52416-11-philmd@linaro.org>
| -rw-r--r-- | target/arm/cpu.c | 3 | ||||
| -rw-r--r-- | target/arm/tcg/cpu-v7m.c | 3 |
2 files changed, 2 insertions, 4 deletions
diff --git a/target/arm/cpu.c b/target/arm/cpu.c index cacbbc6..d7e61d0 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -830,7 +830,6 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, static bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { - CPUClass *cc = CPU_GET_CLASS(cs); CPUARMState *env = cpu_env(cs); uint32_t cur_el = arm_current_el(env); bool secure = arm_is_secure(env); @@ -930,7 +929,7 @@ static bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) found: cs->exception_index = excp_idx; env->exception.target_el = target_el; - cc->tcg_ops->do_interrupt(cs); + cs->cc->tcg_ops->do_interrupt(cs); return true; } diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c index 29a41fd..c4dd309 100644 --- a/target/arm/tcg/cpu-v7m.c +++ b/target/arm/tcg/cpu-v7m.c @@ -19,7 +19,6 @@ static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { - CPUClass *cc = CPU_GET_CLASS(cs); ARMCPU *cpu = ARM_CPU(cs); CPUARMState *env = &cpu->env; bool ret = false; @@ -35,7 +34,7 @@ static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) if (interrupt_request & CPU_INTERRUPT_HARD && (armv7m_nvic_can_take_pending_exception(env->nvic))) { cs->exception_index = EXCP_IRQ; - cc->tcg_ops->do_interrupt(cs); + cs->cc->tcg_ops->do_interrupt(cs); ret = true; } return ret; |