aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorFea.Wang <fea.wang@sifive.com>2024-06-06 21:54:50 +0800
committerAlistair Francis <alistair.francis@wdc.com>2024-06-26 22:52:24 +1000
commit0c2d5f7396d73a957ba665d7824c9ee7926c0357 (patch)
tree00a0c380e5430bf7422c68c1bbda3f2ce301d092
parenta1a8e7768f321232cff276817adf37e116ba8423 (diff)
downloadqemu-0c2d5f7396d73a957ba665d7824c9ee7926c0357.zip
qemu-0c2d5f7396d73a957ba665d7824c9ee7926c0357.tar.gz
qemu-0c2d5f7396d73a957ba665d7824c9ee7926c0357.tar.bz2
target/riscv: Define macros and variables for ss1p13
Add macros and variables for RISC-V privilege 1.13 support. Signed-off-by: Fea.Wang <fea.wang@sifive.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Weiwei Li <liwei1518@gmail.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240606135454.119186-3-fea.wang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
-rw-r--r--target/riscv/cpu.h4
-rw-r--r--target/riscv/cpu_cfg.h1
2 files changed, 4 insertions, 1 deletions
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index b4c9e13..90b8f1b 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -96,12 +96,14 @@ extern RISCVCPUProfile *riscv_profiles[];
#define PRIV_VER_1_10_0_STR "v1.10.0"
#define PRIV_VER_1_11_0_STR "v1.11.0"
#define PRIV_VER_1_12_0_STR "v1.12.0"
+#define PRIV_VER_1_13_0_STR "v1.13.0"
enum {
PRIV_VERSION_1_10_0 = 0,
PRIV_VERSION_1_11_0,
PRIV_VERSION_1_12_0,
+ PRIV_VERSION_1_13_0,
- PRIV_VERSION_LATEST = PRIV_VERSION_1_12_0,
+ PRIV_VERSION_LATEST = PRIV_VERSION_1_13_0,
};
#define VEXT_VERSION_1_00_0 0x00010000
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index e1e4f32..fb7eebd 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -136,6 +136,7 @@ struct RISCVCPUConfig {
* TCG always implement/can't be user disabled,
* based on spec version.
*/
+ bool has_priv_1_13;
bool has_priv_1_12;
bool has_priv_1_11;