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author | Weiwei Li <liweiwei@iscas.ac.cn> | 2022-07-18 21:09:50 +0800 |
---|---|---|
committer | Alistair Francis <alistair.francis@wdc.com> | 2022-09-07 09:18:32 +0200 |
commit | 0b572c8131998e7bcd048dbbbe78f95e6101d68d (patch) | |
tree | 012c0dc378cf2409a38328fb0237daadc2737b7b | |
parent | e4b4f0b71ccbeb0157489c0904ba4957761528ff (diff) | |
download | qemu-0b572c8131998e7bcd048dbbbe78f95e6101d68d.zip qemu-0b572c8131998e7bcd048dbbbe78f95e6101d68d.tar.gz qemu-0b572c8131998e7bcd048dbbbe78f95e6101d68d.tar.bz2 |
target/riscv: Add check for supported privilege mode combinations
There are 3 suggested privilege mode combinations listed in section 1.2
of the riscv-privileged spec(draft-20220717):
1) M, 2) M, U 3) M, S, U
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-Id: <20220718130955.11899-2-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
-rw-r--r-- | target/riscv/cpu.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index a3e4e24..b919ad9 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -721,6 +721,12 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) return; } + if (cpu->cfg.ext_s && !cpu->cfg.ext_u) { + error_setg(errp, + "Setting S extension without U extension is illegal"); + return; + } + if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) { error_setg(errp, "F extension requires Zicsr"); return; |