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authorPhilippe Mathieu-Daudé <philmd@linaro.org>2025-03-31 16:46:13 +0200
committerPhilippe Mathieu-Daudé <philmd@linaro.org>2025-03-31 21:32:43 +0200
commit04e99f9eb7920b0f0fcce65686c3bedf5e32a1f9 (patch)
tree75b109c0adce110a92a3ef90e9acf40654ff6af2
parentc458f9474d6574505ce9144ab1a90b951e69c1bd (diff)
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hw/pci-host/designware: Fix ATU_UPPER_TARGET register access
Fix copy/paste error writing to the ATU_UPPER_TARGET register, we want to update the upper 32 bits. Cc: qemu-stable@nongnu.org Reported-by: Joey <jeundery@gmail.com> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2861 Fixes: d64e5eabc4c ("pci: Add support for Designware IP block") Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Gustavo Romero <gustavo.romero@linaro.org> Message-Id: <20250331152041.74533-2-philmd@linaro.org>
-rw-r--r--hw/pci-host/designware.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c
index c07740b..5598d18 100644
--- a/hw/pci-host/designware.c
+++ b/hw/pci-host/designware.c
@@ -371,7 +371,7 @@ static void designware_pcie_root_config_write(PCIDevice *d, uint32_t address,
case DESIGNWARE_PCIE_ATU_UPPER_TARGET:
viewport->target &= 0x00000000FFFFFFFFULL;
- viewport->target |= val;
+ viewport->target |= (uint64_t)val << 32;
break;
case DESIGNWARE_PCIE_ATU_LIMIT: